EPM3064AT100-10N vs EPM3064ATC100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3064AT100-10N sa pamamagitan ng Altera at EPM3064ATC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3064AT100-10N EPM3064ATC100-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 64
Logic Array Blocks (LABs) 4 —
Usable Gates 1,250 —
User I/O Pins 66 34
Speed Grade -10 (10 ns pin-to-pin delay) —
Supply Voltage (VCCINT) 3.3 V 3.3 V
I/O Bank Voltage 3.3 V —
5 V Tolerant Inputs Yes (via clamping diodes) —
Configuration Memory EEPROM (non-volatile) —
Programming Interface JTAG (IEEE Std. 1149.1) with pin-locking —
ISP Compliance IEEE Std. 1532 —
Boundary-Scan Test (BST) IEEE Std. 1149.1 compliant —
Packhaging TQFP-100 (T100), 14 mm x 14 mm TQFP-100 (100-pin Thin Quad Flat Pack)
Operating Temperature (Commercial) 0C to +70C —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance]
Lead-Free [DATA_NEEDED: lead-free finish] —
Logic Gates — 1250 gates
Logic Array Blocks — 2
Propagation Delay (tPD) — 10 ns
Process Technology — CMOS EEPROM
In-System Programmability — IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant
Global Clock Signals — 2 (with optional inversion)
Output Enable Signals — 6 or 10 pin- or logic-driven
Output Slew-Rate Control — Programmable
Operating Temperature Grade — Commercial
MultiVolt I/O Support — 1.5V / 1.8V / 2.5V / 3.3V interfaces

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