EPM3128ATC100-5 vs EPM3128ATC100-10NS Comparison

Detailed side-by-side comparison of EPM3128ATC100-5 by Intel and EPM3128ATC100-10NS by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3128ATC100-5 EPM3128ATC100-10NS
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Series MAX 3000A —
Family CPLD - MAX 3000A MAX 3000A
Macrocells 128 —
Usable Gates 2,500 —
User I/Os 80 80
Dedicated Inputs 4 —
Pin-to-Pin Delay (tpd) 5 ns (commercial); 7.5 ns —
Maximum Frequency (fCNT) 192.3 MHz —
Supply Voltage (VCCINT/VCCIO) 3.3 V —
Output Drive Voltage 2.5 V or 3.3 V (programmable) —
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant —
Program Memory Type EEPROM —
In-System Programmability Yes, IEEE Std. 1532 compliant —
JTAG Boundary Scan Yes, IEEE Std. 1149.1 —
Operating Temperature 0 °C to 70 °C (Commercial) [DATA_NEEDED: operating temperature range]
Package 100-pin TQFP (Fine Line) TQFP-100
Mounting Type Surface Mount Surface Mount
Logic Family CMOS —
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Process Technology CMOS EEPROM —
Device Type — CPLD (Complex Programmable Logic Device)
Macro Cells — 128
Pin Count — 100
Pin-to-Pin Logic Delay (tPD) — 10 ns
Counter Frequency (fCNT) — up to 227.3 MHz
Supply Voltage - Core (VCCINT) — 3.3 V
Supply Voltage - I/O (VCCIO) — 3.3 V or 2.5 V (5.0 V-tolerant inputs)
Logic-Level Compatibility — 5.0 V, 3.3 V, 2.5 V
Programmability — In-system (ISP), IEEE Std. 1532
Boundary Scan — IEEE 1149.1 JTAG
Configuration Memory — EEPROM (non-volatile)
Lead-Free — [DATA_NEEDED: lead-free status]

Datasheets & Resources

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