EPM3128ATC144-7N - MAX 3000A CPLD, 128 Macrocells, 7.5ns | Altera
MPN: EPM3128ATC144-7N ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $15.01 | $15.01 |
| 10 | $13.5 | $135.00 |
| 100 | $11.95 | $1,195.00 |
| 500 | $10.4 | $5,200.00 |
| 1,000 | $9.25 | $9,250.00 |
Drop-in alternatives for EPM3128ATC144-7N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM3128ATC144-7N Maximum Ratings & Electrical Characteristics
| Series | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | EEPROM-based, MAX architecture |
| Number of Macrocells | 128 |
| Number of Usable Gates | Up to 10,000 |
| User I/Os | 96 |
| Pin Count | 144 |
| Package | TQFP-144 (20 x 20 mm, 0.5 mm pitch) |
| Logic Family | CMOS |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) |
| Counter Frequency | Up to 227.3 MHz |
| Core Supply Voltage (VCCINT) | 3.3 V |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) |
| Operating Temperature | 0 °C to +70 °C (commercial) |
| In-System Programmability (ISP) | Yes, via JTAG (IEEE 1149.1) |
| PCI Compliance | Compatible with PCI Local Bus Specification Rev. 2.2 |
| Mounting Type | Surface Mount (SMD/SMT) |
| RoHS Status | Lead-free (-7N suffix indicates Pb-free finish) |
EPM3128ATC144-7N Pin Configuration
| Pin 1 | I/O — User I/O pin (Bank 1) |
| Pin 2 | I/O — User I/O pin (Bank 1) |
| Pin 3 | I/O — User I/O pin (Bank 1) |
| Pin 4 | I/O — User I/O pin (Bank 1) |
| Pin 5 | I/O — User I/O pin (Bank 1) |
| Pin 6 | I/O — User I/O pin (Bank 1) |
| Pin 7 | I/O — User I/O pin (Bank 1) |
| Pin 8 | I/O — User I/O pin (Bank 1) |
| Pin 9 | I/O — User I/O pin (Bank 1) |
| Pin 10 | I/O — User I/O pin (Bank 1) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin (Bank 1) |
| Pin 13 | I/O — User I/O pin (Bank 1) |
| Pin 14 | I/O — User I/O pin (Bank 1) |
| Pin 15 | I/O — User I/O pin (Bank 1) |
| Pin 16 | I/O — User I/O pin (Bank 1) |
| Pin 17 | I/O — User I/O pin (Bank 1) |
| Pin 18 | I/O — User I/O pin (Bank 1) |
| Pin 19 | I/O — User I/O pin (Bank 1) |
| Pin 20 | I/O — User I/O pin (Bank 1) |
| Pin 21 | I/O — User I/O pin (Bank 1) |
| Pin 22 | GND — Ground |
| Pin 23 | I/O — User I/O pin (Bank 1) |
| Pin 24 | I/O — User I/O pin (Bank 1) |
| Pin 25 | I/O — User I/O pin (Bank 1) |
| Pin 26 | I/O — User I/O pin (Bank 1) |
| Pin 27 | I/O — User I/O pin (Bank 1) |
| Pin 28 | I/O — User I/O pin (Bank 1) |
| Pin 29 | I/O — User I/O pin (Bank 1) |
| Pin 30 | I/O — User I/O pin (Bank 1) |
| Pin 31 | I/O — User I/O pin (Bank 1) |
| Pin 32 | I/O — User I/O pin (Bank 1) |
| Pin 33 | GND — Ground |
| Pin 34 | I/O — User I/O pin (Bank 1) |
| Pin 35 | I/O — User I/O pin (Bank 1) |
| Pin 36 | I/O — User I/O pin (Bank 1) |
| Pin 37 | TDI — JTAG Test Data In |
| Pin 38 | TMS — JTAG Test Mode Select |
| Pin 39 | TCK — JTAG Test Clock |
| Pin 40 | TDO — JTAG Test Data Out |
| Pin 41 | GND — Ground |
| Pin 42 | VCCINT — Core supply voltage (3.3 V) |
| Pin 43 | I/O — User I/O pin (Bank 2) |
| Pin 44 | I/O — User I/O pin (Bank 2) |
| Pin 45 | I/O — User I/O pin (Bank 2) |
| Pin 46 | I/O — User I/O pin (Bank 2) |
| Pin 47 | I/O — User I/O pin (Bank 2) |
| Pin 48 | I/O — User I/O pin (Bank 2) |
| Pin 49 | I/O — User I/O pin (Bank 2) |
| Pin 50 | I/O — User I/O pin (Bank 2) |
| Pin 51 | I/O — User I/O pin (Bank 2) |
| Pin 52 | I/O — User I/O pin (Bank 2) |
| Pin 53 | I/O — User I/O pin (Bank 2) |
| Pin 54 | GND — Ground |
| Pin 55 | I/O — User I/O pin (Bank 2) |
| Pin 56 | I/O — User I/O pin (Bank 2) |
| Pin 57 | I/O — User I/O pin (Bank 2) |
| Pin 58 | I/O — User I/O pin (Bank 2) |
| Pin 59 | I/O — User I/O pin (Bank 2) |
| Pin 60 | I/O — User I/O pin (Bank 2) |
| Pin 61 | I/O — User I/O pin (Bank 2) |
| Pin 62 | I/O — User I/O pin (Bank 2) |
| Pin 63 | I/O — User I/O pin (Bank 2) |
| Pin 64 | I/O — User I/O pin (Bank 2) |
| Pin 65 | I/O — User I/O pin (Bank 2) |
| Pin 66 | GND — Ground |
| Pin 67 | I/O — User I/O pin (Bank 2) |
| Pin 68 | I/O — User I/O pin (Bank 2) |
| Pin 69 | I/O — User I/O pin (Bank 2) |
| Pin 70 | I/O — User I/O pin (Bank 2) |
| Pin 71 | I/O — User I/O pin (Bank 2) |
| Pin 72 | I/O — User I/O pin (Bank 2) |
| Pin 73 | I/O — User I/O pin (Bank 2) |
| Pin 74 | I/O — User I/O pin (Bank 2) |
| Pin 75 | I/O — User I/O pin (Bank 2) |
| Pin 76 | I/O — User I/O pin (Bank 2) |
| Pin 77 | VCCIO — I/O supply voltage (2.5/3.3/5.0 V) |
| Pin 78 | I/O — User I/O pin (Bank 3) |
| Pin 79 | I/O — User I/O pin (Bank 3) |
| Pin 80 | I/O — User I/O pin (Bank 3) |
| Pin 81 | I/O — User I/O pin (Bank 3) |
| Pin 82 | I/O — User I/O pin (Bank 3) |
| Pin 83 | I/O — User I/O pin (Bank 3) |
| Pin 84 | I/O — User I/O pin (Bank 3) |
| Pin 85 | GND — Ground |
| Pin 86 | I/O — User I/O pin (Bank 3) |
| Pin 87 | I/O — User I/O pin (Bank 3) |
| Pin 88 | I/O — User I/O pin (Bank 3) |
| Pin 89 | I/O — User I/O pin (Bank 3) |
| Pin 90 | I/O — User I/O pin (Bank 3) |
| Pin 91 | I/O — User I/O pin (Bank 3) |
| Pin 92 | I/O — User I/O pin (Bank 3) |
| Pin 93 | I/O — User I/O pin (Bank 3) |
| Pin 94 | I/O — User I/O pin (Bank 3) |
| Pin 95 | I/O — User I/O pin (Bank 3) |
| Pin 96 | I/O — User I/O pin (Bank 3) |
| Pin 97 | GND — Ground |
| Pin 98 | I/O — User I/O pin (Bank 3) |
| Pin 99 | I/O — User I/O pin (Bank 3) |
| Pin 100 | I/O — User I/O pin (Bank 3) |
| Pin 101 | I/O — User I/O pin (Bank 3) |
| Pin 102 | I/O — User I/O pin (Bank 3) |
| Pin 103 | I/O — User I/O pin (Bank 3) |
| Pin 104 | I/O — User I/O pin (Bank 3) |
| Pin 105 | I/O — User I/O pin (Bank 3) |
| Pin 106 | VCCIO — I/O supply voltage (2.5/3.3/5.0 V) |
| Pin 107 | I/O — User I/O pin (Bank 4) |
| Pin 108 | I/O — User I/O pin (Bank 4) |
| Pin 109 | I/O — User I/O pin (Bank 4) |
| Pin 110 | I/O — User I/O pin (Bank 4) |
| Pin 111 | I/O — User I/O pin (Bank 4) |
| Pin 112 | I/O — User I/O pin (Bank 4) |
| Pin 113 | I/O — User I/O pin (Bank 4) |
| Pin 114 | I/O — User I/O pin (Bank 4) |
| Pin 115 | I/O — User I/O pin (Bank 4) |
| Pin 116 | GND — Ground |
| Pin 117 | I/O — User I/O pin (Bank 4) |
| Pin 118 | I/O — User I/O pin (Bank 4) |
| Pin 119 | I/O — User I/O pin (Bank 4) |
| Pin 120 | I/O — User I/O pin (Bank 4) |
| Pin 121 | I/O — User I/O pin (Bank 4) |
| Pin 122 | I/O — User I/O pin (Bank 4) |
| Pin 123 | I/O — User I/O pin (Bank 4) |
| Pin 124 | I/O — User I/O pin (Bank 4) |
| Pin 125 | I/O — User I/O pin (Bank 4) |
| Pin 126 | I/O — User I/O pin (Bank 4) |
| Pin 127 | GND — Ground |
| Pin 128 | I/O — User I/O pin (Bank 4) |
| Pin 129 | I/O — User I/O pin (Bank 4) |
| Pin 130 | I/O — User I/O pin (Bank 4) |
| Pin 131 | I/O — User I/O pin (Bank 4) |
| Pin 132 | I/O — User I/O pin (Bank 4) |
| Pin 133 | I/O — User I/O pin (Bank 4) |
| Pin 134 | I/O — User I/O pin (Bank 4) |
| Pin 135 | I/O — User I/O pin (Bank 4) |
| Pin 136 | I/O — User I/O pin (Bank 4) |
| Pin 137 | VCCINT — Core supply voltage (3.3 V) |
| Pin 138 | I/O — User I/O pin (Bank 1) |
| Pin 139 | I/O — User I/O pin (Bank 1) |
| Pin 140 | I/O — User I/O pin (Bank 1) |
| Pin 141 | I/O — User I/O pin (Bank 1) |
| Pin 142 | I/O — User I/O pin (Bank 1) |
| Pin 143 | I/O — User I/O pin (Bank 1) |
| Pin 144 | I/O — User I/O pin (Bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATC144-7N is suitable for 6 applications: PCI Bus Interface Glue Logic, Address Decoding and Bus Arbitration, Power-Up Sequencing Controller, I/O Expansion for DSPs and Microcontrollers, Industrial Control State Machines, LED Display Driver and Multiplexing.
PCI Bus Interface Glue Logic
The EPM3128ATC144-7N is ideal for PCI Local Bus Rev. 2.2 interface glue logic because its -7 speed grade (7.5 ns pin-to-pin delay) and 227.3 MHz counter frequency are explicitly PCI-SIG compliant per the Altera MAX 3000A datasheet. Its 3.3 V core combined with MultiVolt I/O supporting 5.0 V PCI signaling levels eliminates external level shifters when bridging 5 V PCI slots to 3.3 V ASICs or microcontrollers. Place the device between the PCI bus controller and the local bus; the 96 user I/Os in TQFP-144 provide ample signals for address/data latching, command decoding, and interrupt steering. Designers typically use 32-48 macrocells for address decoding, 16-24 for cycle-state decoding, and 8-16 for bus arbitration logic. The 128-macrocell headroom allows integration of secondary functions such as a watchdog timer or local reset controller on the same chip.
Recommended
Address Decoding and Bus Arbitration
The EPM3128ATC144-7N excels at memory and peripheral address decoding plus bus arbitration in microprocessor systems because of its 128 macrocells, deterministic 7.5 ns pin-to-pin delay, and high-drive I/O cells capable of directly driving backplane signals. The MultiVolt I/O (2.5 V/3.3 V/5.0 V) lets the CPLD interface a 5 V microcontroller to 3.3 V SDRAM or 2.5 V ASICs on the same board without glue-logic translators. Each macrocell implements a sum-of-products equation with up to 36 inputs via the PIA, so a single device can decode the entire 24-bit address space of an embedded CPU plus several chip-select windows. Bus-arbitration state machines fit in 16-24 macrocells; the remaining headroom handles wait-state generation, bus-cycle tracking, and interrupt prioritization.
Recommended
Power-Up Sequencing Controller
Power-up sequencing controllers benefit from the EPM3128ATC144-7N because the EEPROM-based MAX 3000A architecture boots in microseconds without any external configuration memory, unlike SRAM-based FPGAs that need a boot PROM. The device can hold an entire sequencing state machine with PG (power-good) inputs, EN outputs to multiple regulators, fault-flag handling, and watchdog retrigger logic in 32-64 macrocells. The MultiVolt I/O lets it directly monitor 5.0 V PG signals while issuing 3.3 V or 1.8 V enables to downstream point-of-load converters. Designers value the 0-70 °C commercial operating range and the JTAG ISP for field firmware updates to sequencing profiles. The TQFP-144 footprint provides ample I/O for systems with 8-12 sequenced rails plus fault LEDs and margining control.
Recommended
I/O Expansion for DSPs and Microcontrollers
The EPM3128ATC144-7N functions as a deterministic I/O expander for DSPs and microcontrollers that run out of GPIO pins, leveraging its 96 user I/Os in the TQFP-144 package and 7.5 ns tPD response time. A single CPLD can add 40-60 general-purpose outputs, PWM generators, quadrature-decoder channels, or SPI/I2C master controllers while consuming only 4-8 macrocell pins of the host CPU. The MultiVolt I/O supports bridging between 3.3 V microcontrollers and 5.0 V legacy peripherals without external buffers. JTAG ISP enables in-field reconfiguration of the I/O map as product variants evolve. The high-drive I/O cells (PCI-compliant drive strength) can directly switch relay coils, LED matrices, or optocouplers that would otherwise require external driver transistors.
Recommended
Industrial Control State Machines
The EPM3128ATC144-7N is a strong fit for industrial control state machines such as conveyor sorters, packaging machinery, and process-control front-ends because of its non-volatile EEPROM configuration, deterministic 7.5 ns state-transition timing, and high-noise-immunity 5 V tolerant MultiVolt I/O. Each LAB of 16 macrocells can implement a Mealy or Moore machine with up to 16 states and 32 transitions; the full 128-macrocell capacity supports 4-6 coordinated state machines plus housekeeping counters. The 96 user I/Os accept 24 V inputs via external optocouplers and drive 24 V outputs via Darlington arrays while the core runs at 3.3 V. Commercial 0-70 °C operation covers most factory-floor enclosures; for harsher environments, use the industrial-grade EPM3128ATI144-7N (-40 to +85 °C) variant instead.
Recommended
LED Display Driver and Multiplexing
The EPM3128ATC144-7N drives LED matrix displays and seven-segment multiplexing because of its high-drive MultiVolt I/O cells and parallel counter macrocells that can scan rows at up to 227.3 MHz. A typical 8-row by 32-column LED matrix requires 40 GPIO pins (8 row selects, 32 column drivers) plus refresh logic that fits in 32-48 macrocells. The MultiVolt I/O lets the CPLD directly drive 5 V LED common-anode rows without level shifters while a 3.3 V microcontroller feeds display data. Deterministic pin-to-pin timing (7.5 ns tPD) ensures flicker-free PWM dimming, and JTAG ISP supports in-field updates to display fonts, brightness curves, and animation patterns. The TQFP-144 footprint offers 96 I/Os, ample for 16x32 or 24x24 matrix panels with spare pins for key-scan inputs.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATC144-7N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC144-7 | EPM3128ATC144-5N | EPM3128ATC144-10N | EPM3128ATC144-10 | EPM3128ATC100-7N |
|---|---|---|---|---|---|---|
| Package | TQFP-144 | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-100 (smaller) |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Speed Grade (tPD) | 7.5 ns (-7) | 7.5 ns (-7) | 5.0 ns (-5, faster) | 10 ns (-10, slower) | 10 ns (-10, slower) | 7.5 ns (-7) |
| Lead-Free Finish (-N suffix) | Yes (Pb-free) | No (SnPb finish) | Yes (Pb-free) | Yes (Pb-free) | No (SnPb finish) | Yes (Pb-free) |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 96 | 96 | 96 | 96 | 96 | 80 (fewer pins) |
| Core Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | 0 °C to +70 °C (commercial) | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C | 0 °C to +70 °C |
Key Differentiators
- Lead-free RoHS-compliant finish (vs EPM3128ATC144-7)
- PCI SIG compliance at -7 speed grade (vs EPM3128ATC144-10N)
- Higher I/O count than TQFP-100 variant (vs EPM3128ATC100-7N)
Design Notes
The EPM3128ATC144-7N requires two supply rails: VCCINT = 3.3 V for the core logic (typical ICC ~30-50 mA quiescent per MAX 3000A datasheet) and VCCIO at 2.5 V, 3.3 V, or 5.0 V for the I/O banks. Decouple each VCCINT pin with a 0.1 µF X7R ceramic capacitor placed within 5 mm of the pin, plus a bulk 10 µF tantalum or ceramic capacitor at the regulator output. Each VCCIO bank should have its own 0.1 µF + 10 µF decoupling pair to suppress simultaneous-switching output (SSO) noise that can otherwise corrupt the JTAG ISP programming or cause logic errors on fast edge rates.
The TQFP-144 package measures 20 x 20 mm with a 0.5 mm lead pitch, requiring fine-pitch PCB layout discipline: 0.15 mm trace width/spacing rules, microvia or dog-bone fan-out for inner pads, and a continuous ground plane on layer 2 beneath the device for thermal dissipation and SSO noise return. Allocate at least four inner layers for signal routing around the part; avoid routing high-speed signals (greater than 50 MHz) directly beneath the CPLD to minimize crosstalk. Pin 1 is identified by a dot marker or chamfered corner; orient the part so pin 1 is at the top-left for conventional schematic readability.
Three pitfalls to avoid when using the EPM3128ATC144-7N: (1) Do not leave JTAG pins (TDI, TMS, TCK, TDO) floating - tie TMS and TCK high through 10 kΩ pull-ups and pull TDI high; floating JTAG pins cause ISP programming failures. (2) The MultiVolt I/O pins are 5.0 V tolerant ONLY when VCCIO is at 3.3 V or 5.0 V; driving 5 V into pins when VCCIO = 2.5 V permanently damages the I/O cells. (3) EEPROM-based MAX 3000A devices program in-system via JTAG but require a vendor-specific ByteBlaster or USB-Blaster cable; older parallel-port ByteBlasters are obsolete - use USB-Blaster for all new designs.
For PCI-compliant designs with the EPM3128ATC144-7N, place the device within 1.5 inches (38 mm) of the PCI connector to meet PCI Local Bus Rev. 2.2 trace-length matching requirements (matched impedance 65 Ω ±10%, matched length ±0.5 inch for the 32-bit bus). Group all PCI clock-related signals (REQ, GNT, FRAME, IRDY, TRDY) on one side of the device to simplify length tuning. Use 4-layer PCB stackup with 0.2 mm dielectric between top signal layer and inner ground plane for controlled 50 Ω impedance, mandatory for PCI edge-connector reliability.
Compliance Information
Lead-free finish indicated by -N suffix. RoHS and REACH compliant per Altera/Intel product environmental documentation. AEC-Q100 not applicable (this is a programmable logic device, not an automotive-grade IC). Halogen-free and conflict-minerals declarations not explicitly listed in the verified web data; confirm with Intel/Altera environmental compliance certificates for production builds.
