EPM3512AFC256-10 vs EPM3512AFC256-18 Comparison
Detailed side-by-side comparison of EPM3512AFC256-10 by Altera and EPM3512AFC256-18 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM3512AFC256-18 - MAX 3000A CPLD, 512 Macrocells, BGA-256 | Altera
EPM3512AFC256-18 ObsoleteSpecification Comparison
| Parameter | EPM3512AFC256-10 | EPM3512AFC256-18 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.50 | $17.20 |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Usable Gates | 10,000 | β |
| Maximum I/O Pins | 208 | β |
| Pin-to-Pin Delay (tPD) | 10 ns | β |
| Maximum Counter Frequency | 87 MHz | β |
| Supply Voltage (VCCINT) | 3.3 V | β |
| I/O Voltage Tolerance | 5-V tolerant | β |
| Programmable Technology | CMOS EEPROM | β |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) | β |
| Package | 256-pin FBGA | 256-ball FineLine BGA (FCBGA) |
| Operating Temperature Range | [DATA_NEEDED: industrial/commercial operating temperature range] | β |
| Pin Count | 256 | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | unknown | [DATA_NEEDED: not specified in retrieved data] |
| Architecture | MAX (Multiple Array matriX) EEPROM-based | β |
| Maximum User I/O Pins | β | 212 |
| Pin-to-Pin Delay (tPD1) | β | 18 ns |
| Global Clock Networks | β | 4 |
| VCCINT (Core Supply) | β | 3.0 V to 3.6 V (3.3 V typical) |
| VCCIO (I/O Supply) | β | 2.5 V or 3.3 V (MultiVolt) |
| Operating Temperature | β | [DATA_NEEDED: industrial/commercial grade] |
| Programming Technology | β | EEPROM (non-volatile) |
| In-System Programming | β | IEEE Std. 1532 / JTAG (IEEE Std. 1149.1) |
| Ball Pitch | β | 1.0 mm |