EPM3512AFC256-22 vs EPM3512AFC256-23 Comparison

Detailed side-by-side comparison of EPM3512AFC256-22 by Intel and EPM3512AFC256-23 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AFC256-22 EPM3512AFC256-23
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $16.10 $15.75
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) β€”
Macrocells 512 512
Logic Array Blocks (LABs) 16 16 (32 macrocells each)
Maximum User I/O Pins 208 (typical for FC256 package) β€”
Speed Grade -22 (tPD ~22 ns) β€”
Propagation Delay (tPD) 22 ns 5.5 ns
Supply Voltage VCCINT 3.3 V β€”
I/O Standards Supported 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) β€”
In-System Programming IEEE Std. 1532-compliant ISP via JTAG β€”
Configuration Memory On-chip EEPROM (non-volatile) β€”
Package FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) 256-ball FineLine BGA (FC256), 17 mm x 17 mm
Mounting Type Surface Mount (BGA) Surface Mount (BGA)
Operating Temperature [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: operating temperature grade]
RoHS Status [DATA_NEEDED: RoHS compliance status] β€”
Usable Gates β€” 10,000
Maximum Operating Frequency β€” 178.6 MHz
Pin-to-Pin Delay β€” 23 ns
Supply Voltage (VCCINT) β€” 3.3 V
I/O Supply Voltage (VCCIO) β€” 2.5 V / 3.3 V / 5.0 V (MultiVolt)
User I/O Pins β€” [DATA_NEEDED: user I/O count for FC256]
Programming Interface β€” JTAG (IEEE Std. 1149.1) / ISP
Process Technology β€” 0.30 Β΅m CMOS EEPROM

Datasheets & Resources

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