EPM3512AQC20810N vs EPM3256AQC208-10N Comparison

Detailed side-by-side comparison of EPM3512AQC20810N by Altera and EPM3256AQC208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM3512AQC20810N EPM3256AQC208-10N
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 512 —
Usable Gates 10,000 10,000
User I/Os 172 —
Logic Array Blocks (LABs) 16 —
Propagation Delay (tPD) 10 ns —
Core Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 3.3 V (5.0 V tolerant I/O) —
Package 208-pin PQFP (Plastic Quad Flat Pack) —
Configuration Memory EEPROM (non-volatile, instant-on) —
Programming Interface JTAG (IEEE 1149.1 / IEEE 1532 ISP) —
Maximum Frequency [DATA_NEEDED: fMAX] —
Operating Temperature [DATA_NEEDED: industrial/commercial grade range] 0C to +70C (Commercial)
RoHS Status [DATA_NEEDED: lead-free/RoHS status] [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]
Mounting Type Surface Mount Surface Mount
MSL Level [DATA_NEEDED: MSL rating] —
Series — MAX 3000A
Programmable Type — In-System Programmable (EEPROM)
Number of Macrocells — 256
Number of Logic Elements/Blocks — 16 LABs
Number of I/O Pins — 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) — 10 ns (max)
Maximum Counter Frequency — 227.3 MHz
Supply Voltage - Internal — 3.0 V to 3.6 V (3.3 V typical)
Package / Case — 208-BFQFP / 208-PQFP (28x28 mm)
ISP Compliance — IEEE Std. 1532
Boundary Scan — IEEE Std. 1149.1 (JTAG)
I/O Tolerance — 5 V tolerant, MultiVolt interface

Datasheets & Resources

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