EPM3512AQC20810N vs EPM3256AQC208-10N 对比

详细并排对比 EPM3512AQC20810N 出自 Altera 和 EPM3256AQC208-10N 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

规格对比

参数 EPM3512AQC20810N EPM3256AQC208-10N
品牌 Altera Altera
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 不推荐新设计 Obsolete
库存状态 有库存 有库存
单价(USD) $39.75 $4.62
Family MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) —
Macro Cells 512 —
Usable Gates 10,000 10,000
User I/Os 172 —
Logic Array Blocks (LABs) 16 —
Propagation Delay (tPD) 10 ns —
Core Voltage (VCCINT) 3.3 V —
I/O Voltage (VCCIO) 3.3 V (5.0 V tolerant I/O) —
封装 208-pin PQFP (Plastic Quad Flat Pack) —
Configuration Memory EEPROM (non-volatile, instant-on) —
Programming Interface JTAG (IEEE 1149.1 / IEEE 1532 ISP) —
Maximum Frequency [DATA_NEEDED: fMAX] —
工作温度 [DATA_NEEDED: industrial/commercial grade range] 0C to +70C (Commercial)
RoHS 状态 [DATA_NEEDED: lead-free/RoHS status] [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data]
安装类型 Surface Mount Surface Mount
MSL 等级 [DATA_NEEDED: MSL rating] —
Series — MAX 3000A
Programmable Type — In-System Programmable (EEPROM)
Number of Macrocells — 256
Number of Logic Elements/Blocks — 16 LABs
Number of I/O Pins — 161 (158 user I/O per Arrow listing)
Propagation Delay (tpd) — 10 ns (max)
Maximum Counter Frequency — 227.3 MHz
Supply Voltage - Internal — 3.0 V to 3.6 V (3.3 V typical)
封装 / 外壳 — 208-BFQFP / 208-PQFP (28x28 mm)
ISP Compliance — IEEE Std. 1532
Boundary Scan — IEEE Std. 1149.1 (JTAG)
I/O Tolerance — 5 V tolerant, MultiVolt interface

数据手册与资源

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