EPM5032DC-25 vs EPM5032JC25 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5032DC-25 disebabkan oleh Altera dan EPM5032JC25 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5032DC-25 EPM5032JC25
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Manufacturer Altera (Intel Programmable Solutions Group) —
Product Family MAX 5000 —
Device Type UV Erasable Programmable Logic Device (EPLD) —
Macrocells 32 —
Pin-to-Pin Propagation Delay (tPD) 25 ns —
Maximum Counter Frequency (fCNT) [DATA_NEEDED: maximum counter frequency] —
Setup Time (tSU) [DATA_NEEDED: setup time] —
Number of Dedicated Inputs 32 (in DIP-28 pinout) —
Number of I/O Pins 22 (in DIP-28 pinout, 4 used as dedicated inputs) —
Kemasan CDIP-28 (Windowed Ceramic DIP-28) 28-pin PLCC (JC)
Process Technology CMOS, EPROM (UV-Erasable) —
Architecture PAL-Type, Single-LAB, 32-Macrocell PAL-type macrocells with global Programmable Interconnect Array (PIA)
Output Structure Programmable I/O with output enable —
Flip-Flop Configuration D, T, JK, or SR (programmable) —
Suhu Operasi [DATA_NEEDED: operating temperature range] —
Status RoHS Lead Free / RoHS Compliant (per distributor listings) [DATA_NEEDED: RoHS status]
Programming Method UV erase + Altera/Intel MAX+PLUS II programmer —
Erasure Method UV light through ceramic window —
Family — MAX 5000
Device — EPM5032
Logic Elements — 32 macrocells
Propagation Delay (tPD) — 25 ns
Maximum Internal Frequency — 62.5 MHz
Product Terms — 320
Flip-Flops — 32
Dedicated Inputs — 7
Bidirectional I/O Pins — 16
Total Inputs to Array — 24
Bilangan Output — 16
Technology — CMOS EPROM, UV-erasable (windowed) / OTP
Tegangan Pemberi Arus — 5 V (TTL-level I/O)
Jenis Pemasangan — Surface Mount

Laporan Datasheet & Sumber

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