EPM5032SC-20 vs EPM5032PC-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032SC-20 sa pamamagitan ng Altera at EPM5032PC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032SC-20 EPM5032PC-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Device Type EPLD (Erasable Programmable Logic Device) EPLD (Erasable PLD)
Family MAX 5000 —
Macrocells 32 —
Dedicated Inputs 7 7
I/O Pins 16 —
Outputs 16 —
Propagation Delay (tPD) 20 ns 15 ns
Speed Grade -20 (20 ns) 15 (15 ns tPD)
Architecture PAL-type, CMOS, UV-erasable —
Interconnect Programmable Interconnect Array (PIA) —
Packhaging 20-pin SOIC (Small Outline) 28-pin PDIP (PC suffix = windowed CerDIP)
Temperature na Operasyon 0 °C to +70 °C (commercial grade) 0C to +70C (commercial)
Uri ng Pagpapasok Surface Mount Through-Hole (DIP)
Volte ng Pagbibigay [DATA_NEEDED: VCC typical range] —
Technology CMOS EPROM cell —
Programmability One-time programmable (windowless SOIC) —
Tindminan RoHS [DATA_NEEDED: RoHS status not confirmed in verified data] Non-compliant (CerDIP window, contains Be)
Device Family — MAX 5000
Macro Cells — 32
Usable Gates — 600
Logic Elements / LABs — 1 LAB (4 macrocells per group)
Maximum Internal Frequency — 76.9 MHz (some sources list 83.3 MHz)
Operating Voltage (VCC) — 5 V (typ.)
Technology Node — 0.8 micron CMOS
Configuration Memory — UV-Erasable EPROM
Bidirectional I/O Pins — 16
Total Array Inputs — 24
Pin/Package Suffix — PC = Windowed Ceramic DIP
Programming Tool — Altera Logic Programmer + MAX+plus II
Lead-Free — No

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