EPM5064JC vs EPM5064JC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064JC sa pamamagitan ng Altera at EPM5064JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064JC EPM5064JC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) —
Macrocells 64 64
Usable Gates 1,250 (approx.) 1250
Logic Array Inputs 36 —
Logic Array Outputs 64 —
Packhaging 68-pin PLCC (JEDEC) 28-pin CLCC (J-lead, ceramic, windowed)
Uri ng Pagpapasok Surface Mount (socketed) —
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) 5 V (4.75 V to 5.25 V)
I/O Logic Level TTL / CMOS compatible —
Configuration Memory EPROM (UV-erasable window or OTP) —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] [DATA_NEEDED: commercial or industrial grade]
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] —
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] —
Lead-Free [DATA_NEEDED: lead-free status] —
Level ng MSL [DATA_NEEDED: MSL rating] —
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) —
Logic Array Blocks (LABs) — 4
Propagation Delay (tPD) — 45 ns
Maximum Clock Frequency (fMAX) — 50 MHz
Dedicated Inputs — 7
I/O Pins — 28
Interconnect — Programmable Interconnect Array (PIA)
Technology — CMOS, UV-erasable EPROM
Programming Method — UV-erase + EPROM programmer (not ISP)
Compliance — RoHS status unknown (ceramic/J-lead windowed part, legacy product)

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