EPM5064JC vs EPM5064LC-2 Comparison
Detailed side-by-side comparison of EPM5064JC by Altera and EPM5064LC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5064JC | EPM5064LC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $8.40 |
| Family | MAX 5000 | β |
| Device Type | EPLD (Erasable PLD) | β |
| Macrocells | 64 | 64 |
| Usable Gates | 1,250 (approx.) | β |
| Logic Array Inputs | 36 | β |
| Logic Array Outputs | 64 | β |
| Package | 68-pin PLCC (JEDEC) | PLCC-44 (J-Lead, plastic) |
| Mounting Type | Surface Mount (socketed) | Surface Mount |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Level | TTL / CMOS compatible | β |
| Configuration Memory | EPROM (UV-erasable window or OTP) | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | β |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | β |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not specified in source] |
| Lead-Free | [DATA_NEEDED: lead-free status] | β |
| MSL Level | [DATA_NEEDED: MSL rating] | β |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | β |
| Device Family | β | MAX 5000 |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | β | 4 |
| Logic Elements per LAB | β | 16 |
| Number of Inputs | β | 36 (7 dedicated + 28 I/O) |
| Number of I/O Pins | β | 28 |
| Number of Flip-Flops | β | 28 |
| Propagation Delay (tPD) | β | 45 ns |
| Maximum Internal Frequency | β | 40 MHz |
| Process Technology | β | CMOS, OTP EPROM (UV-erasable base) |
| Programmable Polarity | β | Yes |
| Programmable Output Enable | β | Yes, per macrocell |
| Programming Method | β | Altera byte-wide / JTAG programmer |