EPM5064JC vs EPM5064LC-2 比較
詳細並排比較 EPM5064JC 由 Altera 與 EPM5064LC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064JC | EPM5064LC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable PLD) | — |
| Macrocells | 64 | 64 |
| Usable Gates | 1,250 (approx.) | — |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| 封裝 | 68-pin PLCC (JEDEC) | PLCC-44 (J-Lead, plastic) |
| 安裝類型 | Surface Mount (socketed) | Surface Mount |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | 4.75 V to 5.25 V (5 V nominal) |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source] |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not specified in source] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Device Family | — | MAX 5000 |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 |
| Logic Elements per LAB | — | 16 |
| Number of Inputs | — | 36 (7 dedicated + 28 I/O) |
| Number of I/O Pins | — | 28 |
| Number of Flip-Flops | — | 28 |
| Propagation Delay (tPD) | — | 45 ns |
| Maximum Internal Frequency | — | 40 MHz |
| Process Technology | — | CMOS, OTP EPROM (UV-erasable base) |
| Programmable Polarity | — | Yes |
| Programmable Output Enable | — | Yes, per macrocell |
| Programming Method | — | Altera byte-wide / JTAG programmer |