EPM5128JC-1 vs EPM5128LC-1 Comparison
Detailed side-by-side comparison of EPM5128JC-1 by Altera and EPM5128LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM5128LC-1
EPM5128LC-1 - 128-Macrocell MAX 5000 CPLD | Altera | 5V 68-Pin PLCC
EPM5128LC-1 ObsoleteSpecification Comparison
| Parameter | EPM5128JC-1 | EPM5128LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $24.95 | $8.20 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Erasable Programmable Logic Device (EPLD/CPLD) | β |
| Macrocells | 128 | β |
| Usable Gates | 2,500 | β |
| Logic Array Blocks (LABs) | [DATA_NEEDED: LAB count] | β |
| Maximum Operating Frequency | 62.5 MHz | β |
| Pin-to-Pin Propagation Delay (tPD) | 40 ns | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (Β±10%) |
| Technology | CMOS, UV-erasable EPROM | β |
| Package | 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) | β |
| Mounting Type | Surface Mount | Surface Mount (J-lead PLCC socket compatible) |
| Operating Temperature | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Programming Interface | JTAG / Altera dedicated programmer | β |
| Configuration Memory | Non-volatile EPROM (UV-erasable) | β |
| RoHS Status | non_compliant (ceramic windowed package) | [DATA_NEEDED: RoHS status] |
| Lifecycle Status | Obsolete - last-time-buy inventory only | β |
| Logic Elements / Macrocells | β | 128 macrocells |
| Number of Usable Gates | β | [DATA_NEEDED: usable gates] |
| Dedicated Inputs | β | 7 |
| Bidirectional I/O Pins | β | 52 |
| Total User I/O | β | 60 (max) |
| Propagation Delay (tpd) | β | 30 ns |
| Process Technology | β | CMOS EPROM, UV-erasable |
| Programmability | β | UV-erasable / OTP (windowed package) |
| Package Type | β | 68-pin J-lead ceramic chip carrier (PLCC windowed) |
| JTAG Support | β | IEEE 1149.1 boundary-scan |
| Lead-Free | β | [DATA_NEEDED: lead-free status] |