EPM5128JC-1 vs EPM5128LC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128JC-1 sa pamamagitan ng Altera at EPM5128LC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128JC-1 EPM5128LC-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type Erasable Programmable Logic Device (EPLD/CPLD) —
Macrocells 128 —
Usable Gates 2,500 —
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Maximum Operating Frequency 62.5 MHz —
Pin-to-Pin Propagation Delay (tPD) 40 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (±10%)
Technology CMOS, UV-erasable EPROM —
Packhaging 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) —
Uri ng Pagpapasok Surface Mount Surface Mount (J-lead PLCC socket compatible)
Temperature na Operasyon [DATA_NEEDED: temperature grade] 0C to +70C (commercial)
Programming Interface JTAG / Altera dedicated programmer —
Configuration Memory Non-volatile EPROM (UV-erasable) —
Tindminan RoHS non_compliant (ceramic windowed package) [DATA_NEEDED: RoHS status]
Katayuan ng Lifecycle Obsolete - last-time-buy inventory only —
Logic Elements / Macrocells — 128 macrocells
Number of Usable Gates — [DATA_NEEDED: usable gates]
Dedicated Inputs — 7
Bidirectional I/O Pins — 52
Total User I/O — 60 (max)
Propagation Delay (tpd) — 30 ns
Process Technology — CMOS EPROM, UV-erasable
Programmability — UV-erasable / OTP (windowed package)
Package Type — 68-pin J-lead ceramic chip carrier (PLCC windowed)
JTAG Support — IEEE 1149.1 boundary-scan
Lead-Free — [DATA_NEEDED: lead-free status]

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