EPM5128JC-1 vs EPM5128LC-1 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5128JC-1 disebabkan oleh Altera dan EPM5128LC-1 disebabkan oleh Altera. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5128JC-1 EPM5128LC-1
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type Erasable Programmable Logic Device (EPLD/CPLD) —
Macrocells 128 —
Usable Gates 2,500 —
Logic Array Blocks (LABs) [DATA_NEEDED: LAB count] —
Maximum Operating Frequency 62.5 MHz —
Pin-to-Pin Propagation Delay (tPD) 40 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (±10%)
Technology CMOS, UV-erasable EPROM —
Kemasan 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier) —
Jenis Pemasangan Surface Mount Surface Mount (J-lead PLCC socket compatible)
Suhu Operasi [DATA_NEEDED: temperature grade] 0C to +70C (commercial)
Programming Interface JTAG / Altera dedicated programmer —
Configuration Memory Non-volatile EPROM (UV-erasable) —
Status RoHS non_compliant (ceramic windowed package) [DATA_NEEDED: RoHS status]
Status Lingkungan Hidup Obsolete - last-time-buy inventory only —
Logic Elements / Macrocells — 128 macrocells
Number of Usable Gates — [DATA_NEEDED: usable gates]
Dedicated Inputs — 7
Bidirectional I/O Pins — 52
Total User I/O — 60 (max)
Propagation Delay (tpd) — 30 ns
Process Technology — CMOS EPROM, UV-erasable
Programmability — UV-erasable / OTP (windowed package)
Package Type — 68-pin J-lead ceramic chip carrier (PLCC windowed)
JTAG Support — IEEE 1149.1 boundary-scan
Lead-Free — [DATA_NEEDED: lead-free status]

Laporan Datasheet & Sumber

Lihat Semua Produk Buat BOQ Minta Bao Harga