EPM5128JC-2 vs EPM5128LC-1 Perbandingan
Perbandingan bersamaan detil EPM5128JC-2 dari Altera dan EPM5128LC-1 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5128JC-2 | EPM5128LC-1 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) | — |
| Macrocells | 128 | — |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tPD) | 45 ns (max) | — |
| Maximum Counter Frequency (fCNT) | 50 MHz | — |
| Input Setup Time (tSU) | 7.5 ns | — |
| Output Drive Current (IOH/IOL) | 12 mA DC | — |
| Process Technology | CMOS | CMOS EPROM, UV-erasable |
| Paket | 68-pin CQCC (Ceramic Quad Flat Pack), windowed | — |
| Tipe Mounting | Surface Mount | Surface Mount (J-lead PLCC socket compatible) |
| Suhu Kerja | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Tegangan Pemuat | 5 V (nominal) | — |
| Program/Erase Method | UV (ceramic window) | — |
| Erase/Program Cycles | [DATA_NEEDED: minimum erase/program cycles] | — |
| Status RoHS | Non-compliant (ceramic windowed package contains lead-bearing solder) | [DATA_NEEDED: RoHS status] |
| Logic Family | TTL-compatible I/O | — |
| Logic Elements / Macrocells | — | 128 macrocells |
| Number of Usable Gates | — | [DATA_NEEDED: usable gates] |
| Bidirectional I/O Pins | — | 52 |
| Total User I/O | — | 60 (max) |
| Propagation Delay (tpd) | — | 30 ns |
| Supply Voltage (VCC) | — | 5 V (±10%) |
| Programmability | — | UV-erasable / OTP (windowed package) |
| Package Type | — | 68-pin J-lead ceramic chip carrier (PLCC windowed) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |