EPM5128JC-2 - 128-Macrocell UV PLD, 45ns, CQCC-68 | Altera
MPN: EPM5128JC-2 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.9 | $2,890.00 |
| 500 | $24.5 | $12,250.00 |
| 1,000 | $21.75 | $21,750.00 |
Drop-in alternatives for EPM5128JC-2 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM5128JC-1
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View Datasheet →EPM5128JC-2 Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Device Type | UV-Erasable Programmable Logic Device (PLD) |
| Macrocells | 128 |
| Dedicated Inputs | 7 |
| Propagation Delay (tPD) | 45 ns (max) |
| Maximum Counter Frequency (fCNT) | 50 MHz |
| Input Setup Time (tSU) | 7.5 ns |
| Output Drive Current (IOH/IOL) | 12 mA DC |
| Process Technology | CMOS |
| Package | 68-pin CQCC (Ceramic Quad Flat Pack), windowed |
| Mounting Type | Surface Mount |
| Supply Voltage | 5 V (nominal) |
| Program/Erase Method | UV (ceramic window) |
| RoHS Status | Non-compliant (ceramic windowed package contains lead-bearing solder) |
| Logic Family | TTL-compatible I/O |
EPM5128JC-2 Pin Configuration
| Pin 1 | DIP7 — Dedicated input 7 |
| Pin 2 | DIP6 — Dedicated input 6 |
| Pin 3 | DIP5 — Dedicated input 5 |
| Pin 4 | DIP4 — Dedicated input 4 |
| Pin 5 | DIP3 — Dedicated input 3 |
| Pin 6 | DIP2 — Dedicated input 2 |
| Pin 7 | DIP1 — Dedicated input 1 |
| Pin 8 | GND — Ground |
| Pin 9 | I/O — Bidirectional I/O pin |
| Pin 10 | I/O — Bidirectional I/O pin |
| Pin 11 | I/O — Bidirectional I/O pin |
| Pin 12 | I/O — Bidirectional I/O pin |
| Pin 13 | I/O — Bidirectional I/O pin |
| Pin 14 | I/O — Bidirectional I/O pin |
| Pin 15 | I/O — Bidirectional I/O pin |
| Pin 16 | I/O — Bidirectional I/O pin |
| Pin 17 | I/O — Bidirectional I/O pin |
| Pin 18 | I/O — Bidirectional I/O pin |
| Pin 19 | I/O — Bidirectional I/O pin |
| Pin 20 | I/O — Bidirectional I/O pin |
| Pin 21 | VCC — +5V supply |
| Pin 22 | I/O — Bidirectional I/O pin |
| Pin 23 | I/O — Bidirectional I/O pin |
| Pin 24 | I/O — Bidirectional I/O pin |
| Pin 25 | I/O — Bidirectional I/O pin |
| Pin 26 | I/O — Bidirectional I/O pin |
| Pin 27 | I/O — Bidirectional I/O pin |
| Pin 28 | I/O — Bidirectional I/O pin |
| Pin 29 | I/O — Bidirectional I/O pin |
| Pin 30 | I/O — Bidirectional I/O pin |
| Pin 31 | I/O — Bidirectional I/O pin |
| Pin 32 | I/O — Bidirectional I/O pin |
| Pin 33 | I/O — Bidirectional I/O pin |
| Pin 34 | GND — Ground |
| Pin 35 | I/O — Bidirectional I/O pin |
| Pin 36 | I/O — Bidirectional I/O pin |
| Pin 37 | I/O — Bidirectional I/O pin |
| Pin 38 | I/O — Bidirectional I/O pin |
| Pin 39 | I/O — Bidirectional I/O pin |
| Pin 40 | I/O — Bidirectional I/O pin |
| Pin 41 | I/O — Bidirectional I/O pin |
| Pin 42 | I/O — Bidirectional I/O pin |
| Pin 43 | I/O — Bidirectional I/O pin |
| Pin 44 | I/O — Bidirectional I/O pin |
| Pin 45 | I/O — Bidirectional I/O pin |
| Pin 46 | I/O — Bidirectional I/O pin |
| Pin 47 | I/O — Bidirectional I/O pin |
| Pin 48 | VCC — +5V supply |
| Pin 49 | I/O — Bidirectional I/O pin |
| Pin 50 | I/O — Bidirectional I/O pin |
| Pin 51 | I/O — Bidirectional I/O pin |
| Pin 52 | I/O — Bidirectional I/O pin |
| Pin 53 | I/O — Bidirectional I/O pin |
| Pin 54 | I/O — Bidirectional I/O pin |
| Pin 55 | I/O — Bidirectional I/O pin |
| Pin 56 | I/O — Bidirectional I/O pin |
| Pin 57 | I/O — Bidirectional I/O pin |
| Pin 58 | I/O — Bidirectional I/O pin |
| Pin 59 | I/O — Bidirectional I/O pin |
| Pin 60 | I/O — Bidirectional I/O pin |
| Pin 61 | GND — Ground |
| Pin 62 | I/O — Bidirectional I/O pin |
| Pin 63 | I/O — Bidirectional I/O pin |
| Pin 64 | I/O — Bidirectional I/O pin |
| Pin 65 | I/O — Bidirectional I/O pin |
| Pin 66 | I/O — Bidirectional I/O pin |
| Pin 67 | I/O — Bidirectional I/O pin |
| Pin 68 | I/O — Bidirectional I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5128JC-2 is suitable for 6 applications: Legacy 5V Bus Glue Logic, Address Decoder for Microprocessor Systems, State Machine Controller (Industrial Automation), DMA Controller / Bus Arbiter, VME / Multibus II Backplane Interface, Military / Aerospace Long-Lifecycle System.
Legacy 5V Bus Glue Logic
The EPM5128JC-2 fits 5V bus-interface glue logic applications because its 128 macrocells, 45 ns tPD, and TTL-compatible I/O directly support address decoding, chip-select generation, and wait-state insertion for legacy 8/16-bit buses. Placed between a 68000 or 8086 microprocessor and peripheral memory, the 45 ns tPD satisfies the 200 ns 68000 bus cycle when registered logic adds one clock of latency. Unlike a discrete 74LS/74F TTL decoder array, the EPM5128JC-2 consolidates a full board's worth of glue logic into one 128-macrocell device, freeing PCB area. The CQCC-68 ceramic package is also ruggedized for industrial and military environments where commercial plastic PLD packages would be inadequate.
Recommended
Address Decoder for Microprocessor Systems
The EPM5128JC-2 is well suited to 24-bit address decoder applications because its 128 macrocells can implement 8-12 independent chip-select outputs with overlapping address windows, replacing 4-6 standard 74LS138/139 decoders. With 45 ns tPD, the worst-case decoder latency through one PLD level is 45 ns, well within a 100 ns 8086 read cycle budget. The 7 dedicated inputs are useful for routing read/write/address-strobe signals globally to every macrocell. Compared to discrete TTL decoders, the EPM5128JC-2 reduces board area by ~70 percent and simplifies design changes since the address map is reprogrammable in software rather than requiring a PCB spin.
Recommended
State Machine Controller (Industrial Automation)
The EPM5128JC-2 fits industrial state-machine controller applications because 128 macrocells can hold 8-12 complex FSMs with 8-16 states each, while 45 ns tPD supports state-transition frequencies up to 22 MHz for high-speed sorting or motion-control logic. Its 50 MHz fCNT figure is more than adequate for sequencing stepper motors, solenoid valves, and conveyor actuators. The windowed ceramic CQCC package tolerates the wide temperature and humidity swings of factory floors better than plastic parts. According to the MAX 5000 datasheet, the 7 dedicated inputs are ideal for global asynchronous-clear and clock-enable signals common to industrial state machines.
Recommended
DMA Controller / Bus Arbiter
The EPM5128JC-2 is appropriate for legacy DMA and bus arbitration logic because 128 macrocells can implement a multi-master round-robin or priority arbiter, bus-request/grant state machines, and transfer counters. Its 45 ns tPD supports arbitration decisions within one 50 ns VME or Multibus clock cycle, which is critical for high-throughput DMA. The 12 mA DC output drive directly interfaces TTL peripherals without external buffers. Compared to a discrete arbiter built from 74LS/74AS logic, the EPM5128JC-2 implements the entire arbiter in one device, simplifying debug and allowing late changes to priority schemes via in-circuit reprogramming (with UV erasure).
Recommended
VME / Multibus II Backplane Interface
The EPM5128JC-2 is well matched to VME and Multibus II backplane interface applications because its 128 macrocells can implement a complete bus-interface handler including address decoding, interrupt acknowledge, bus-error timeout, and DTACK generation. The 45 ns tPD is fast enough for 8 MHz VMEbus (125 ns cycle) and 10 MHz Multibus II (100 ns cycle) bus protocols. The windowed ceramic CQCC-68 package meets the long-term reliability requirements of industrial and military backplane systems. The 5 V TTL-compatible I/O directly drives the VMEbus backplane transceivers without level translation.
Recommended
Military / Aerospace Long-Lifecycle System
The EPM5128JC-2 is used in military and aerospace long-lifecycle applications because the windowed ceramic CQCC package supports up to 1000 UV erase/program cycles, allowing field firmware updates on deployed equipment. The same 128-macrocell die is available in 883B-screened variants (EPM5128GM/883B) for Class B and Class S military qualification. The ceramic CQCC package is hermetically sealed, qualifying it for high-altitude, humidity, and vibration environments. According to the Altera datasheet, the MAX 5000 architecture is rated for -55C to +125C operation in military variants, making it ideal for avionics and weapons-platform subsystems that must remain in service for 20-30 years.
Recommended
Recommended Products Summary
Engineering reference data for EPM5128JC-2 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5128JC-1 | EPM5128JC | EPM5128GM/883B | EPM5128GC-2 | EPM5128GC-1 | EPM5128GC | EPM5128GI |
|---|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 68-pin CQCC (windowed ceramic) | 68-pin CQCC (windowed ceramic) - same | 68-pin CQCC (windowed ceramic) - same | 68-pin ceramic pin grid equivalent - same footprint | 68-pin CQCC (non-windowed ceramic) - same | 68-pin CQCC (non-windowed ceramic) - same | 68-pin CQCC (non-windowed ceramic) - same | 68-pin CQCC (industrial temp ceramic) - same |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 45 ns | 35 ns | 45 ns | 45 ns | 45 ns | 35 ns | 45 ns | 45 ns |
| Windowed (UV-erasable) | Yes | Yes | Yes | Yes | No (OTP) | No (OTP) | No (OTP) | No (OTP) |
| Speed Grade | -2 (45 ns) | -1 (35 ns) | No suffix (45 ns) | -2 (45 ns, military screened) | -2 (45 ns) | -1 (35 ns) | No suffix (45 ns) | Industrial temp |
| Military Grade (883B) | No (commercial) | No | No | Yes | No | No | No | No |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete (military long-term support) | Obsolete | Obsolete | Obsolete | Obsolete |
| Typical Unit Price (1 pc, as of 2026-09-12) | $38.50 | Higher (faster grade) | Similar ($36-40) | Higher (military screening) | Lower (non-windowed) | Lower (non-windowed, faster) | Lower (non-windowed) | Higher (industrial temp) |
Key Differentiators
- Windowed ceramic package allows field re-programmability (vs EPM5128GC-2 (non-windowed ceramic OTP version))
- -2 speed grade for mid-speed applications (vs EPM5128JC-1 (faster 35 ns -1 grade))
- Maximum 128-macrocell density in MAX 5000 family (vs EPM5064JC (64 macrocells, half the density))
- Commercial temperature grade, lowest cost in windowed MAX 5000 (vs EPM5128GM/883B (military-screened windowed ceramic))
Design Notes
The EPM5128JC-2 has 7 dedicated inputs that are NOT usable as I/O pins. Designers must subtract these from the available I/O count when planning pin allocation. The 7 dedicated inputs are typically used for global clock, clock enable, asynchronous clear, and output enable signals that need to be routed to every macrocell. Failing to budget for these dedicated pins is a common mistake when porting designs from generic PLDs to the MAX 5000 family.
Estimated: At maximum toggle frequency (50 MHz fCNT) with all 48 I/O pins driving 12 mA loads, the EPM5128JC-2 in the 68-pin CQCC ceramic package dissipates approximately 1.0-1.5 W. The CQCC ceramic package has good thermal performance with a theta_JA of roughly 30-40 C/W due to the ceramic substrate, so junction temperature rise is around 30-50 C above ambient at typical operating conditions. Designers should still provide adequate PCB copper area and verify junction temperature with a thermal probe in production builds for high-reliability applications.
When migrating from the J-suffix windowed ceramic CQCC-68 to the L-suffix plastic PLCC-68 (EPM5128LC-2), the PCB footprint is NOT 1:1. The ceramic CQCC has JEDEC-standard ceramic-flat-pack land patterns with 1.27 mm pitch gull-wing leads, while the PLCC-68 has J-leads on a slightly different pad geometry. The package outline differs in body size (CQCC-68 ~24x24 mm vs PLCC-68 ~24x24 mm) and lead bend style. Use the appropriate JEDEC land pattern from the Altera datasheet for the target package. Many legacy designs mount the J-package on a through-hole socket to allow easy removal and UV erasure during development.
The EPM5128JC-2's 45 ns tPD is for a single combinational path through one macrocell. Multi-level logic paths add propagation delays linearly, so a 3-macrocell decoder chain has approximately 3 x 45 ns = 135 ns total delay. Designers should keep critical-speed paths within 2 macrocell levels (90 ns) to stay within VME/8086 bus cycle budgets. Registered outputs add one flip-flop clock-to-Q delay (typically 10-15 ns) but break the combinational delay chain, which is often faster overall for deep logic. According to the MAX 5000 datasheet, registered macrocells also consume 1 dedicated input for the global clock.
Compliance Information
Windowed ceramic CQCC package uses lead-bearing solder for the ceramic lid seal, exempt from RoHS under exemption 7(b) for lead in ceramic electronic components. Not qualified to AEC-Q100 (automotive) standard. REACH, halogen-free, and conflict-mineral compliance status not stated in manufacturer datasheet.
