EPM5128JC-2 vs EPM5128LC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128JC-2 sa pamamagitan ng Altera at EPM5128LC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128JC-2 EPM5128LC-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type UV-Erasable Programmable Logic Device (PLD) —
Macrocells 128 —
Dedicated Inputs 7 7
Propagation Delay (tPD) 45 ns (max) —
Maximum Counter Frequency (fCNT) 50 MHz —
Input Setup Time (tSU) 7.5 ns —
Output Drive Current (IOH/IOL) 12 mA DC —
Process Technology CMOS CMOS EPROM, UV-erasable
Packhaging 68-pin CQCC (Ceramic Quad Flat Pack), windowed —
Uri ng Pagpapasok Surface Mount Surface Mount (J-lead PLCC socket compatible)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Volte ng Pagbibigay 5 V (nominal) —
Program/Erase Method UV (ceramic window) —
Erase/Program Cycles [DATA_NEEDED: minimum erase/program cycles] —
Tindminan RoHS Non-compliant (ceramic windowed package contains lead-bearing solder) [DATA_NEEDED: RoHS status]
Logic Family TTL-compatible I/O —
Logic Elements / Macrocells — 128 macrocells
Number of Usable Gates — [DATA_NEEDED: usable gates]
Bidirectional I/O Pins — 52
Total User I/O — 60 (max)
Propagation Delay (tpd) — 30 ns
Supply Voltage (VCC) — 5 V (±10%)
Programmability — UV-erasable / OTP (windowed package)
Package Type — 68-pin J-lead ceramic chip carrier (PLCC windowed)
JTAG Support — IEEE 1149.1 boundary-scan
Lead-Free — [DATA_NEEDED: lead-free status]

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