EPM5128JC vs EPM5128JC-1 Comparison

Detailed side-by-side comparison of EPM5128JC by Altera and EPM5128JC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5128JC EPM5128JC-1
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $24.95
Product Family MAX 5000 β€”
Device Type EPLD / CPLD Erasable Programmable Logic Device (EPLD/CPLD)
Macrocell Count 128 β€”
Propagation Delay (tPD) 35 ns β€”
Logic Elements Programmable AND/OR/XOR array β€”
Supply Voltage (VCC) 5 V (typical) 4.75 V to 5.25 V (5 V nominal)
Number of Pins 68 β€”
Package Type PLCC-68 (JLCC) ceramic, J-leaded β€”
Dedicated Inputs 8 β€”
User I/O Pins [DATA_NEEDED: user I/O pin count] β€”
Configuration Memory UV-erasable EPROM (windowed package) Non-volatile EPROM (UV-erasable)
Programming Interface Altera MAX+PLUS II / A+PLUS / legacy programmer JTAG / Altera dedicated programmer
Operating Temperature Commercial 0C to +70C [DATA_NEEDED: temperature grade]
Mounting Type Surface Mount (PLCC socket or solder) Surface Mount
Boundary Scan JTAG IEEE 1149.1 (family feature) β€”
Process Technology CMOS EPROM β€”
RoHS Status [DATA_NEEDED: RoHS status - legacy part] non_compliant (ceramic windowed package)
Lead-Free [DATA_NEEDED: lead-free status] β€”
Family β€” MAX 5000
Macrocells β€” 128
Usable Gates β€” 2,500
Logic Array Blocks (LABs) β€” [DATA_NEEDED: LAB count]
Maximum Operating Frequency β€” 62.5 MHz
Pin-to-Pin Propagation Delay (tPD) β€” 40 ns
Technology β€” CMOS, UV-erasable EPROM
Package β€” 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier)
Lifecycle Status β€” Obsolete - last-time-buy inventory only

Datasheets & Resources

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