EPM5128JC vs EPM5128JC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128JC sa pamamagitan ng Altera at EPM5128JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128JC EPM5128JC-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Family MAX 5000 —
Device Type EPLD / CPLD Erasable Programmable Logic Device (EPLD/CPLD)
Macrocell Count 128 —
Propagation Delay (tPD) 35 ns —
Logic Elements Programmable AND/OR/XOR array —
Supply Voltage (VCC) 5 V (typical) 4.75 V to 5.25 V (5 V nominal)
Bilang ng Pins 68 —
Package Type PLCC-68 (JLCC) ceramic, J-leaded —
Dedicated Inputs 8 —
User I/O Pins [DATA_NEEDED: user I/O pin count] —
Configuration Memory UV-erasable EPROM (windowed package) Non-volatile EPROM (UV-erasable)
Programming Interface Altera MAX+PLUS II / A+PLUS / legacy programmer JTAG / Altera dedicated programmer
Temperature na Operasyon Commercial 0C to +70C [DATA_NEEDED: temperature grade]
Uri ng Pagpapasok Surface Mount (PLCC socket or solder) Surface Mount
Boundary Scan JTAG IEEE 1149.1 (family feature) —
Process Technology CMOS EPROM —
Tindminan RoHS [DATA_NEEDED: RoHS status - legacy part] non_compliant (ceramic windowed package)
Lead-Free [DATA_NEEDED: lead-free status] —
Family — MAX 5000
Macrocells — 128
Usable Gates — 2,500
Logic Array Blocks (LABs) — [DATA_NEEDED: LAB count]
Maximum Operating Frequency — 62.5 MHz
Pin-to-Pin Propagation Delay (tPD) — 40 ns
Technology — CMOS, UV-erasable EPROM
Packhaging — 68-pin CQCCJ (Windowed Ceramic J-Lead Chip Carrier)
Katayuan ng Lifecycle — Obsolete - last-time-buy inventory only

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