EPM5130JC-1 vs EPM5130QC-1 Comparison
Detailed side-by-side comparison of EPM5130JC-1 by Altera and EPM5130QC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5130JC-1 | EPM5130QC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | UV-Erasable / OTP Complex PLD (CPLD) |
| Family | MAX 5000 | MAX 5000 |
| Usable Gates | 2,500 gates | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Dedicated Inputs | 19 | — |
| I/O Pins | 80 | — |
| Package | 84-pin PLCC (J-lead) | PQFP-100 (windowed ceramic) |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Technology | UV-erasable EPROM (quartz window) | — |
| Process Technology | CMOS | CMOS |
| Operating Temperature | 0C to +70C (commercial) | Commercial (0 C to +70 C) |
| External Clock Pins | 1 global clock | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: rohs status] |
| Logic Cells / Macrocells | — | 128 macrocells |
| Usable Gates (marketing) | — | 5130 gates |
| Speed Grade | — | -1 |
| Terminal Pitch | — | 0.635 mm |
| Configuration Memory | — | UV-Erasable EPROM |
| Supply Voltage | — | 5 V (single) |
| Programmable Polarity | — | Yes (per macrocell) |
| Boundary Scan / JTAG | — | Per MAX 5000 family |