EPM5192-1LC vs EPM51929C Comparison

Detailed side-by-side comparison of EPM5192-1LC by Altera and EPM51929C by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192-1LC EPM51929C
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $19.40 $9.40
Family MAX 5000 β€”
Device Type CPLD (Complex Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Usable Gates 3,750 β€”
Macrocells 192 β€”
Logic Array Blocks (LABs) 4 β€”
User I/O Pins 64 β€”
Maximum Operating Frequency 62.5 MHz β€”
Propagation Delay (tpd) [DATA_NEEDED: -1 speed grade tpd in ns] β€”
Supply Voltage 5 V [DATA_NEEDED: VCC range]
Process Technology UV EPROM, erasable windowless β€”
Programmable Interconnect PIA (Programmable Interconnect Array) β€”
JTAG Boundary Scan IEEE 1149.1 compliant β€”
Package 64-pin Ceramic J-Lead Chip Carrier (LC) β€”
Mounting Type Surface Mount Surface Mount or Through-Hole (package dependent)
Operating Temperature 0C to +70C (commercial) Commercial (0C to +70C)
RoHS Status Non-compliant (ceramic windowless package, lead-bearing termination) unknown
Device Family β€” MAX 5000
Architecture β€” Multi-array matrix (PAL-based macrocells)
Logic Density β€” [DATA_NEEDED: usable gates]
Number of Macrocells β€” [DATA_NEEDED: macrocell count]
Number of Pins β€” [DATA_NEEDED: pin count]
Package Type β€” [DATA_NEEDED: package suffix - C denotes commercial temperature grade]
Technology β€” CMOS EPROM
Programmability β€” UV-erasable, JEDEC fuse map
Propagation Delay β€” [DATA_NEEDED: tpd specification]
Maximum Toggle Frequency β€” [DATA_NEEDED: fmax]
Lead-Free β€” unknown
MSL Level β€” [DATA_NEEDED]

Datasheets & Resources

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