EPM5192-1LC vs EPM51929C 比較
詳細並排比較 EPM5192-1LC 由 Altera 與 EPM51929C 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192-1LC | EPM51929C |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 64 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tpd) | [DATA_NEEDED: -1 speed grade tpd in ns] | — |
| 供應電壓 | 5 V | [DATA_NEEDED: VCC range] |
| Process Technology | UV EPROM, erasable windowless | — |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| 封裝 | 64-pin Ceramic J-Lead Chip Carrier (LC) | — |
| 安裝類型 | Surface Mount | Surface Mount or Through-Hole (package dependent) |
| 工作溫度 | 0C to +70C (commercial) | Commercial (0C to +70C) |
| RoHS 狀態 | Non-compliant (ceramic windowless package, lead-bearing termination) | unknown |
| Device Family | — | MAX 5000 |
| Architecture | — | Multi-array matrix (PAL-based macrocells) |
| Logic Density | — | [DATA_NEEDED: usable gates] |
| Number of Macrocells | — | [DATA_NEEDED: macrocell count] |
| 腳位數 | — | [DATA_NEEDED: pin count] |
| Package Type | — | [DATA_NEEDED: package suffix - C denotes commercial temperature grade] |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, JEDEC fuse map |
| Propagation Delay | — | [DATA_NEEDED: tpd specification] |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fmax] |
| Lead-Free | — | unknown |
| MSL 等級 | — | [DATA_NEEDED] |