EPM5192-1LC vs EPM51929C तुलना
विस्तृत दोनों ओर की तुलना EPM5192-1LC द्वारा Altera और EPM51929C द्वारा Intel. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
विशेषता तुलना
| पैरामीटर | EPM5192-1LC | EPM51929C |
|---|---|---|
| ब्रांड | Altera | Intel |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 4 | — |
| User I/O Pins | 64 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tpd) | [DATA_NEEDED: -1 speed grade tpd in ns] | — |
| सप्लाई वोल्टेज | 5 V | [DATA_NEEDED: VCC range] |
| Process Technology | UV EPROM, erasable windowless | — |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| पैकेज | 64-pin Ceramic J-Lead Chip Carrier (LC) | — |
| माउंटिंग प्रकार | Surface Mount | Surface Mount or Through-Hole (package dependent) |
| ऑपरेटिंग तापमान | 0C to +70C (commercial) | Commercial (0C to +70C) |
| RoHS स्थिति | Non-compliant (ceramic windowless package, lead-bearing termination) | unknown |
| Device Family | — | MAX 5000 |
| Architecture | — | Multi-array matrix (PAL-based macrocells) |
| Logic Density | — | [DATA_NEEDED: usable gates] |
| Number of Macrocells | — | [DATA_NEEDED: macrocell count] |
| पिन की संख्या | — | [DATA_NEEDED: pin count] |
| Package Type | — | [DATA_NEEDED: package suffix - C denotes commercial temperature grade] |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, JEDEC fuse map |
| Propagation Delay | — | [DATA_NEEDED: tpd specification] |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fmax] |
| Lead-Free | — | unknown |
| MSL स्तर | — | [DATA_NEEDED] |