EPM5192JC-ES vs EPM5192JC1 Pengandingan

Pengandingan Sisi Kiri Sisi Kanan Terperinci EPM5192JC-ES disebabkan oleh Intel dan EPM5192JC1 disebabkan oleh Intel. Bandingkan spesifikasi utama, parameter elektrik, pakej, status kehidupan, harga, dan keupayaan untuk menentukan komponen terbaik untuk keperluan disenjaya anda.

Pengandingan Spesifikasi

Parametr EPM5192JC-ES EPM5192JC1
Merek Intel Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Device Family MAX 5000 —
Device Type CPLD (EPLD) —
Macrocells 192 —
Logic Array Blocks (LABs) 12 —
Interconnect Programmable Interconnect Array (PIA) —
Configuration Memory EPROM (UV-erasable, one-time programmable for JC-ES) —
Kemasan 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) [DATA_NEEDED: exact package from datasheet]
Jenis Pemasangan Surface Mount [DATA_NEEDED: surface mount or through-hole]
Technology CMOS —
Programming Altera MAX+PLUS II or compatible programmer —
Suhu Operasi [DATA_NEEDED: operating temperature range for ES grade] [DATA_NEEDED: operating temp range]
Tegangan Pemberi Arus [DATA_NEEDED: VCC nominal] —
User I/O Pins [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] —
Status RoHS [DATA_NEEDED: RoHS compliance] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
Aras MSL [DATA_NEEDED: MSL rating] —
Note Datasheet source: Altera MAX 5000 family document, 52 pages —
Family — MAX 5000 (MAX 5xxx CPLD)
Manufacturer — Intel (formerly Altera Corporation)
Macro Cells — 192
Usable Gates — 3750
Maximum Operating Frequency — 62.5 MHz
Supply Voltage (VCC) — 5 V (nominal)
Process Technology — 0.5 µm CMOS, UV-erasable EPROM
Propagation Delay (typ) — [DATA_NEEDED: propagation delay in ns]
I/O Pins — [DATA_NEEDED: I/O pin count]
Programming Interface — JTAG-compatible (Altera MAX 5xxx)
Logic Blocks (LABs) — 24 (8 macrocells per LAB)
AEC-Q100 — not_applicable
Lifecycle — Obsolete - last-time-buy stock only at franchised distributors

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