EPM5192JC-ES vs EPM5192JC1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-ES sa pamamagitan ng Intel at EPM5192JC1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC-ES | EPM5192JC1 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Device Type | CPLD (EPLD) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Configuration Memory | EPROM (UV-erasable, one-time programmable for JC-ES) | — |
| Packhaging | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) | [DATA_NEEDED: exact package from datasheet] |
| Uri ng Pagpapasok | Surface Mount | [DATA_NEEDED: surface mount or through-hole] |
| Technology | CMOS | — |
| Programming | Altera MAX+PLUS II or compatible programmer | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range for ES grade] | [DATA_NEEDED: operating temp range] |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC nominal] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Note | Datasheet source: Altera MAX 5000 family document, 52 pages | — |
| Family | — | MAX 5000 (MAX 5xxx CPLD) |
| Manufacturer | — | Intel (formerly Altera Corporation) |
| Macro Cells | — | 192 |
| Usable Gates | — | 3750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Process Technology | — | 0.5 µm CMOS, UV-erasable EPROM |
| Propagation Delay (typ) | — | [DATA_NEEDED: propagation delay in ns] |
| I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Programming Interface | — | JTAG-compatible (Altera MAX 5xxx) |
| Logic Blocks (LABs) | — | 24 (8 macrocells per LAB) |
| AEC-Q100 | — | not_applicable |
| Lifecycle | — | Obsolete - last-time-buy stock only at franchised distributors |