EPM5192JI-2 vs EPM5192JC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JI-2 sa pamamagitan ng Altera at EPM5192JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JI-2 | EPM5192JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | — |
| Dedicated Inputs | 12 | 7 |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | — |
| Packhaging | JLCC-68 (J-Lead Ceramic) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Temperature na Operasyon | 0C to +70C (commercial) | — |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | — |
| Volte ng Pagbibigay | 5 V (typical) | — |
| Process Technology | CMOS EPROM | CMOS |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS compliance] |
| Katayuan ng Lifecycle | Obsolete (legacy Altera MAX 5000 family) | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| User I/O Pins | — | 64 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns |
| Maksimum na Taktiko ng Oras | — | 40 MHz |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |