EPM5192JI-2 vs EPM5192JC-2 Perbandingan
Perbandingan bersamaan detil EPM5192JI-2 dari Altera dan EPM5192JC-2 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5192JI-2 | EPM5192JC-2 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Usable Gates | 5000 | — |
| Dedicated Inputs | 12 | 7 |
| Flip-Flops | 192 | — |
| Speed Grade | -2 | — |
| Paket | JLCC-68 (J-Lead Ceramic) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Suhu Kerja | 0C to +70C (commercial) | — |
| Programming Technology | UV-Erasable EPROM | — |
| Architecture | Sum-of-products with Programmable Interconnect Array (PIA) | — |
| Tegangan Pemuat | 5 V (typical) | — |
| Process Technology | CMOS EPROM | CMOS |
| Tipe Mounting | Surface Mount | Surface Mount |
| Status RoHS | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS compliance] |
| Status Lingkungan Hidup | Obsolete (legacy Altera MAX 5000 family) | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| User I/O Pins | — | 64 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns |
| Frekuensi Bawah Maximum | — | 40 MHz |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| Rentang Suhu Kerja | — | [DATA_NEEDED: operating temperature range] |