EPM5192LC-2N vs EPM5192LC2 Comparison
Detailed side-by-side comparison of EPM5192LC-2N by Altera and EPM5192LC2 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-2N | EPM5192LC2 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Flip-Flops | 192 | — |
| Logic Elements | 192 macrocells (PAL/GAL-style AND-OR array) | — |
| Package Type | LC (ceramic J-leaded, windowed UV-erasable package family) | — |
| Speed Grade | -2 (tPD approximately 25 ns) | — |
| Propagation Delay (typical) | 25 ns | — |
| Supply Voltage | 5 V (typical) | — |
| Programmability | UV-erasable EPROM cell | — |
| Mounting Type | Surface Mount (LC package) | Surface Mount |
| Operating Temperature | Commercial (0C to +70C) - inferred from speed-grade -2 designation | [DATA_NEEDED: operating temperature range] |
| RoHS Status | Compliant (per -N lead-free suffix) | — |
| Lead-Free | Yes (per -N suffix) | — |
| Architecture | Programmable Logic Array (PLA) with global PIA | — |
| Programming Interface | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| User I/O Pins | — | 64 |
| Logic Array Blocks (LABs) | — | 12 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tpd) | — | 45 ns (LC-2 speed grade) |
| Maximum Clock Frequency | — | 50 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Package | — | PQCC-84 (84-pin Plastic J-Lead Chip Carrier) |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Reprogrammability | — | Windowed UV-erasable (ceramic package variants) / One-time programmable (plastic) |