EPM5192LC-2N vs EPM5192LC2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-2N sa pamamagitan ng Altera at EPM5192LC2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LC-2N EPM5192LC2
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Macrocells 192 192
Flip-Flops 192 —
Logic Elements 192 macrocells (PAL/GAL-style AND-OR array) —
Package Type LC (ceramic J-leaded, windowed UV-erasable package family) —
Speed Grade -2 (tPD approximately 25 ns) —
Propagation Delay (typical) 25 ns —
Volte ng Pagbibigay 5 V (typical) —
Programmability UV-erasable EPROM cell —
Uri ng Pagpapasok Surface Mount (LC package) Surface Mount
Temperature na Operasyon Commercial (0C to +70C) - inferred from speed-grade -2 designation [DATA_NEEDED: operating temperature range]
Tindminan RoHS Compliant (per -N lead-free suffix) —
Lead-Free Yes (per -N suffix) —
Architecture Programmable Logic Array (PLA) with global PIA —
Programming Interface Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) —
Device Type — EPLD (Erasable Programmable Logic Device)
User I/O Pins — 64
Logic Array Blocks (LABs) — 12
Dedicated Inputs — 7
External Clock Inputs — 1
Propagation Delay (tpd) — 45 ns (LC-2 speed grade)
Maksimum na Taktiko ng Oras — 50 MHz
Supply Voltage (VCC) — 5 V
Process Technology — CMOS
Packhaging — PQCC-84 (84-pin Plastic J-Lead Chip Carrier)
Programmable Interconnect — Programmable Interconnect Array (PIA)
Reprogrammability — Windowed UV-erasable (ceramic package variants) / One-time programmable (plastic)

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