EPM5192LC-35 vs EPM5192JC-2 Comparison
Detailed side-by-side comparison of EPM5192LC-35 by Altera and EPM5192JC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-35 | EPM5192JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Series | MAX 5000 | — |
| Family | MAX 5000 CPLD | — |
| Logic Elements / Macrocells | 192 macrocells | — |
| Pin-to-Pin Delay (tPD) | 35 ns | — |
| Speed Grade | -35 | — |
| Programmable Type | UV-Erasable / OTP (EPROM-based) | — |
| Package Type | JLCC (J-Lead Ceramic Chip Carrier) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Logic Voltage | 5 V TTL-compatible I/O | — |
| Operating Temperature | Commercial (0C to +70C) per LC suffix | — |
| Programming Method | Altera legacy programmer (EPROM-based) | UV-erase / EPROM |
| Architecture | LAB-based with Programmable Interconnect Array (PIA) | — |
| I/O Standard | TTL | — |
| RoHS Status | Non-compliant (ceramic hermetic package) | [DATA_NEEDED: RoHS compliance] |
| Lifecycle Status | Obsolete - last-time-buy stock only | — |
| Datasheet Document | Altera MAX 5000 family datasheet (per alldatasheet.com) | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns |
| Maximum Clock Frequency | — | 40 MHz |
| Process Technology | — | CMOS |
| Package | — | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Number of Terminals | — | 84 |
| Operating Temperature Range | — | [DATA_NEEDED: operating temperature range] |