EPM5192LC-35 vs EPM5192JC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-35 sa pamamagitan ng Altera at EPM5192JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LC-35 EPM5192JC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series MAX 5000 —
Family MAX 5000 CPLD —
Logic Elements / Macrocells 192 macrocells —
Pin-to-Pin Delay (tPD) 35 ns —
Speed Grade -35 —
Programmable Type UV-Erasable / OTP (EPROM-based) —
Package Type JLCC (J-Lead Ceramic Chip Carrier) —
Uri ng Pagpapasok Surface Mount Surface Mount
Logic Voltage 5 V TTL-compatible I/O —
Temperature na Operasyon Commercial (0C to +70C) per LC suffix —
Programming Method Altera legacy programmer (EPROM-based) UV-erase / EPROM
Architecture LAB-based with Programmable Interconnect Array (PIA) —
I/O Standard TTL —
Tindminan RoHS Non-compliant (ceramic hermetic package) [DATA_NEEDED: RoHS compliance]
Katayuan ng Lifecycle Obsolete - last-time-buy stock only —
Datasheet Document Altera MAX 5000 family datasheet (per alldatasheet.com) —
Device Family — MAX 5000
Product Type — UV-erasable Programmable Logic Device (PLD)
Macrocells — 192
Logic Array Blocks (LABs) — 12
Interconnect — Programmable Interconnect Array (PIA)
User I/O Pins — 64
Dedicated Inputs — 7
External Clock Inputs — 1
Propagation Delay (tPD) — 45 ns
Maksimum na Taktiko ng Oras — 40 MHz
Process Technology — CMOS
Packhaging — 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed)
Number of Terminals — 84
Hanay ng Temperature na Operasyon — [DATA_NEEDED: operating temperature range]

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