EPM5192LI-1 vs EPM5192LI84 Comparison

Detailed side-by-side comparison of EPM5192LI-1 by Altera and EPM5192LI84 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LI-1 EPM5192LI84
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Family MAX 5000 —
Device Type EPLD (UV-Erasable/OTP Complex PLD) —
Usable Gates 3,750 3,750 gates
Macrocells 192 —
Maximum Toggle Frequency 40 MHz 40 MHz
Supply Voltage 5 V —
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns at -1 grade] —
User I/O Pins [DATA_NEEDED: user I/O count for JLCC variant] 64 (max)
Package Type JLCC (windowed, ceramic, UV-erasable) 84-pin PLCC (J-lead, package code J84/QCCJ)
Process Technology CMOS EPROM, UV-erasable —
Speed Grade -1 —
Operating Temperature [DATA_NEEDED: industrial vs military range] —
Pin Count [DATA_NEEDED: pin count of LI package] —
Mounting Type Surface Mount (JLCC with J-leads) Surface Mount (socket-compatible)
MSL Level [DATA_NEEDED: MSL level] —
RoHS Status [DATA_NEEDED: RoHS status of ceramic LI variant] [DATA_NEEDED: RoHS compliance status]
Lead Free [DATA_NEEDED: lead-free] —
Programmable Interconnect Programmable Interconnect Array (PIA) —
Architecture EEPROM/EPROM-based, non-volatile, instant-on —
Device Family — MAX 5000
Product Type — UV-Erasable/OTP Complex PLD (CPLD)
Macro Cells — 192
Pin-to-Pin Delay (tPD) — 25 ns
Supply Voltage (VCC) — 5 V (single supply)
Operating Temperature Range — -40 °C to +85 °C (industrial)
Configuration Memory — OTP / UV-erasable EPROM
Programming Method — Stand-alone programmer (no JTAG on LI84 OTP variant)
Logic Compatibility — TTL-compatible I/O

Datasheets & Resources

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