EPM5192LI-1 vs EPM5192LI84 比較
詳細並排比較 EPM5192LI-1 由 Altera 與 EPM5192LI84 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LI-1 | EPM5192LI84 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-Erasable/OTP Complex PLD) | — |
| Usable Gates | 3,750 | 3,750 gates |
| Macrocells | 192 | — |
| Maximum Toggle Frequency | 40 MHz | 40 MHz |
| 供應電壓 | 5 V | — |
| Propagation Delay (tPD) | [DATA_NEEDED: tPD in ns at -1 grade] | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for JLCC variant] | 64 (max) |
| Package Type | JLCC (windowed, ceramic, UV-erasable) | 84-pin PLCC (J-lead, package code J84/QCCJ) |
| Process Technology | CMOS EPROM, UV-erasable | — |
| Speed Grade | -1 | — |
| 工作溫度 | [DATA_NEEDED: industrial vs military range] | — |
| 腳位數 | [DATA_NEEDED: pin count of LI package] | — |
| 安裝類型 | Surface Mount (JLCC with J-leads) | Surface Mount (socket-compatible) |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status of ceramic LI variant] | [DATA_NEEDED: RoHS compliance status] |
| Lead Free | [DATA_NEEDED: lead-free] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Architecture | EEPROM/EPROM-based, non-volatile, instant-on | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-Erasable/OTP Complex PLD (CPLD) |
| Macro Cells | — | 192 |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| 工作溫度範圍 | — | -40 °C to +85 °C (industrial) |
| Configuration Memory | — | OTP / UV-erasable EPROM |
| Programming Method | — | Stand-alone programmer (no JTAG on LI84 OTP variant) |
| Logic Compatibility | — | TTL-compatible I/O |