EPM5192LI-1 vs EPM5192LI84 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI-1 sa pamamagitan ng Altera at EPM5192LI84 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LI-1 EPM5192LI84
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 5000 —
Device Type EPLD (UV-Erasable/OTP Complex PLD) —
Usable Gates 3,750 3,750 gates
Macrocells 192 —
Maximum Toggle Frequency 40 MHz 40 MHz
Volte ng Pagbibigay 5 V —
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns at -1 grade] —
User I/O Pins [DATA_NEEDED: user I/O count for JLCC variant] 64 (max)
Package Type JLCC (windowed, ceramic, UV-erasable) 84-pin PLCC (J-lead, package code J84/QCCJ)
Process Technology CMOS EPROM, UV-erasable —
Speed Grade -1 —
Temperature na Operasyon [DATA_NEEDED: industrial vs military range] —
Bilang ng Pin [DATA_NEEDED: pin count of LI package] —
Uri ng Pagpapasok Surface Mount (JLCC with J-leads) Surface Mount (socket-compatible)
Level ng MSL [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: RoHS status of ceramic LI variant] [DATA_NEEDED: RoHS compliance status]
Lead Free [DATA_NEEDED: lead-free] —
Programmable Interconnect Programmable Interconnect Array (PIA) —
Architecture EEPROM/EPROM-based, non-volatile, instant-on —
Device Family — MAX 5000
Product Type — UV-Erasable/OTP Complex PLD (CPLD)
Macro Cells — 192
Pin-to-Pin Delay (tPD) — 25 ns
Supply Voltage (VCC) — 5 V (single supply)
Hanay ng Temperature na Operasyon — -40 °C to +85 °C (industrial)
Configuration Memory — OTP / UV-erasable EPROM
Programming Method — Stand-alone programmer (no JTAG on LI84 OTP variant)
Logic Compatibility — TTL-compatible I/O

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