EPM570GT100I5 vs EPM570T10015 Comparison

Detailed side-by-side comparison of EPM570GT100I5 by Altera and EPM570T10015 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Altera
EPM570GT100I5

EPM570GT100I5 - 570 LE MAX II CPLD, 100-TQFP | Intel / Altera

EPM570GT100I5 βœ“ Active
Altera
EPM570T10015

EPM570T10015 - MAX II CPLD, 570 LEs, TQFP-100 | Intel / Altera

EPM570T10015 βœ“ Active

Specification Comparison

Parameter EPM570GT100I5 EPM570T10015
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Active
Stock Status In Stock In Stock
Unit Price (USD) $4.95 $7.95
Series MAX II β€”
Logic Elements (LE) 570 β€”
Macrocells 440 β€”
Maximum User I/O Pins 76 76
Propagation Delay (tPD) 5.4 ns (typ) β€”
Internal Supply Voltage (VCCINT) 1.71 V to 1.89 V β€”
User I/O Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) β€”
User Flash Memory 8 Kbits 8 Kbits
Programmability In-System Programmable (ISP) via JTAG, non-volatile flash β€”
Configuration Time Instant-On (< 1 ms, no external PROM required) β€”
Operating Temperature -40 C to +100 C (Industrial, "I5") β€”
Package 100-pin TQFP (14x14 mm, 0.5 mm pitch) TQFP-100 (T100) 14 x 14 mm
Mounting Type Surface Mount (Gull-wing leads) β€”
Typical Active Current [DATA_NEEDED: typical active ICC] β€”
Speed Grade GT (fast) β€”
RoHS Status Compliant [DATA_NEEDED: RoHS compliance status]
JTAG Support IEEE 1149.1 boundary scan β€”
Global Clock Networks 4 β€”
Device Family β€” MAX II
Logic Elements β€” 570
Macro Cells β€” 440
Pin-to-Pin Delay (tPD) β€” 15 ns (commercial/industrial speed grade)
Propagation Delay β€” [DATA_NEEDED: detailed tPD/tCO/tSU datasheet values]
Supply Voltage - Core (VCCINT) β€” 3.3 V (2.5 V variants exist in MAX II family)
Supply Voltage - I/O (VCCIO) β€” 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-volt I/O)
Operating Temperature Range β€” -40 Β°C to +85 Β°C (industrial)
Configuration Memory β€” On-chip flash (non-volatile, instant-on)
Programming Interface β€” JTAG (IEEE 1149.1 / IEEE Std 1532)
Supported I/O Standards β€” LVTTL, LVCMOS, PCI, SSTL (per pin)
Process Technology β€” 0.18 Β΅m
MSL Level β€” [DATA_NEEDED: moisture sensitivity level]

Datasheets & Resources

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