EPM570T10015 - MAX II CPLD, 570 LEs, TQFP-100 | Intel / Altera
MPN: EPM570T10015 ✓ Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.25 | $112.50 |
| 100 | $10 | $1,000.00 |
| 500 | $8.9 | $4,450.00 |
| 1,000 | $7.95 | $7,950.00 |
Drop-in alternatives for EPM570T10015 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM570GT100I5N
✅ Drop-In✓ In Stock
$16.5 / Unit
View Datasheet →EPM570GT100C5N
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View Datasheet →EPM570F100I5N
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View Datasheet →EPM570F100C5N
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$5.2 / Unit
View Datasheet →EPM570GT100C5
✅ Drop-In✓ In Stock
$10.95 / Unit
View Datasheet →EPM570GT100I5
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$4.95 / Unit
View Datasheet →EPM570T10015 Maximum Ratings & Electrical Characteristics
| Device Family | MAX II |
| Logic Elements | 570 |
| Macro Cells | 440 |
| User Flash Memory | 8 Kbits |
| Maximum User I/O Pins | 76 |
| Package | TQFP-100 (T100) 14 x 14 mm |
| Pin-to-Pin Delay (tPD) | 15 ns (commercial/industrial speed grade) |
| Supply Voltage - Core (VCCINT) | 3.3 V (2.5 V variants exist in MAX II family) |
| Supply Voltage - I/O (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (multi-volt I/O) |
| Operating Temperature Range | -40 °C to +85 °C (industrial) |
| Configuration Memory | On-chip flash (non-volatile, instant-on) |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE Std 1532) |
| Supported I/O Standards | LVTTL, LVCMOS, PCI, SSTL (per pin) |
| Process Technology | 0.18 µm |
EPM570T10015 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) - bidirectional GPIO, multi-volt standard |
| Pin 2 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 3 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 4 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 5 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 6 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 7 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 8 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 9 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 10 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 13 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 14 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 15 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 16 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 17 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 18 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 19 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 20 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 21 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 22 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 23 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 24 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 25 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 26 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 27 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 28 | GND — Ground |
| Pin 29 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 30 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 31 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 32 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 33 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 34 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 35 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 36 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 37 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 38 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 39 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 40 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 41 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 42 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 43 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 44 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 45 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 46 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 47 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 48 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 49 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 50 | GND — Ground |
| Pin 51 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 52 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 53 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 54 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 55 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 56 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 57 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 58 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 59 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 60 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 61 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 62 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 63 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 64 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 65 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 66 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 67 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 68 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 69 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 70 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 71 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 72 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 73 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 74 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 75 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 76 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 77 | TDI — JTAG Test Data In |
| Pin 78 | TMS — JTAG Test Mode Select |
| Pin 79 | TCK — JTAG Test Clock |
| Pin 80 | TDO — JTAG Test Data Out |
| Pin 81 | nCONFIG — Configuration control (active-low) |
| Pin 82 | nSTATUS — Configuration status (active-low) |
| Pin 83 | CONF_DONE — Configuration done (open-drain) |
| Pin 84 | VCCINT — Core supply voltage (3.3 V) |
| Pin 85 | GND — Ground |
| Pin 86 | VCCIO — I/O bank supply voltage |
| Pin 87 | VCCIO — I/O bank supply voltage |
| Pin 88 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 89 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 90 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 91 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 92 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 93 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 94 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 95 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 96 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 97 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 98 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 99 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
| Pin 100 | I/O — User I/O pin (bank 1) - bidirectional GPIO |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570T10015 is suitable for 7 applications: Industrial Control I/O Expansion, Bus Bridging and Protocol Translation, Power-Sequencing and Supervisory Logic, Motor-Control Signal Conditioning, ASIC/ASSP Replacement Glue Logic, Peripheral I/O Expansion for SoCs, Display and Touch Interface Bridging.
Industrial Control I/O Expansion
The EPM570T10015's 570 logic elements and 76 user I/O pins make it well suited for expanding MCU or SoC GPIO in industrial control systems. The 100-pin TQFP package provides ample I/O for parallel-bus interfaces, sensor-multiplexer control, and isolated digital-input conditioning, while the instant-on flash configuration means no boot delay on cold-start machinery. Industrial temperature rating (-40 to +85 C) is critical for PLC backplanes and motor-drive control cards exposed to factory ambient swings.
Recommended
Bus Bridging and Protocol Translation
The EPM570T10015 is widely used as a glue-logic translator between SPI, I2C, UART, and parallel-bus peripherals that cannot be interfaced directly to a host processor. With 570 LEs it has the capacity to implement multiple protocol state machines concurrently, while the 15 ns pin-to-pin delay suits standard-mode bus speeds without timing closure issues. Multi-volt I/O support (1.5/1.8/2.5/3.3 V) lets the device bridge legacy 5 V-tolerant and modern low-voltage rails in the same design.
Recommended
Power-Sequencing and Supervisory Logic
Power-up and power-down sequencing in multi-rail systems is a classic MAX II use case, and the EPM570T10015 fits this role with deterministic timing and instant-on non-volatile configuration. The 570-LE capacity allows several rail-sequencer state machines plus watchdog logic and reset-distribution trees. Designers typically pair the CPLD with a supervisor or PMIC, using the CPLD to enforce sequence dependencies and fault responses that the PMIC alone cannot implement.
Recommended
Motor-Control Signal Conditioning
In motor-drive electronics, the EPM570T10015 is often used for Hall-sensor decoding, fault-input aggregation, and PWM-signal conditioning between an MCU and the gate driver stage. The 15 ns propagation delay is fast enough to handle encoder feedback in real time, and the 100-pin TQFP package supports the many parallel signals (Hall A/B/C, ENC_A, ENC_B, INDEX, FAULT_n, BRAKE_n) typical of BLDC and stepper systems. The industrial temperature grade suits under-hood automotive and traction environments.
Recommended
ASIC/ASSP Replacement Glue Logic
When a discrete 74-series logic implementation grows beyond a handful of packages, the EPM570T10015 can absorb the entire glue-logic netlist into a single 100-pin TQFP. This reduces PCB area, improves reliability by removing dozens of solder joints, and provides a programmable migration path when interface requirements change. Quartus II/Prime schematic capture lets engineers re-target 74-series symbols directly into the CPLD without HDL rewrite.
Recommended
Peripheral I/O Expansion for SoCs
Modern SoCs often expose high-speed serial interfaces (USB, PCIe, RGMII) but lack parallel GPIO for buttons, LEDs, and legacy peripherals; the EPM570T10015 fills this gap by providing up to 76 user I/O pins with multi-volt support. The non-volatile instant-on behavior means peripherals are available immediately at power-up without waiting for the SoC bootloader. JTAG-based in-system programmability supports field updates without re-balling the SoC.
Recommended
Display and Touch Interface Bridging
The EPM570T10015 can bridge between an application processor and LCD/touch-panel controllers that use legacy parallel RGB or SPI interfaces. Its 570-LE capacity allows pixel-data multiplexing, backlight PWM generation, and touch-event debouncing in a single device. The multi-volt I/O banks permit direct connection to both 1.8 V SoC pads and 3.3 V display-driver pads without level shifters, simplifying the BOM.
Recommended
Recommended Products Summary
Engineering reference data for EPM570T10015 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570GT100I5N | EPM570GT100C5N | EPM570F100I5N | EPM570F100C5N | EPM570GT100C5 | EPM570GT100I5 |
|---|---|---|---|---|---|---|---|
| Package | TQFP-100 (T100) 14 x 14 mm | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same | TQFP-100 (T100) - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 | 570 |
| Speed Grade (tPD) | 15 ns | 5 ns (faster) | 5 ns (faster) | 5 ns (faster) | 5 ns (faster) | 5 ns (faster) | 5 ns (faster) |
| Operating Temperature Range | -40 C to +85 C (industrial) | -40 C to +85 C (industrial) - same | 0 C to +85 C (commercial) | -40 C to +85 C (industrial) - same | 0 C to +85 C (commercial) | 0 C to +85 C (commercial) | -40 C to +85 C (industrial) - same |
| User I/O Pins | 76 | 76 | 76 | 76 | 76 | 76 | 76 |
| User Flash Memory | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits | 8 Kbits |
| Lead-Free / RoHS | [DATA_NEEDED: not confirmed] | Yes (N suffix) | Yes (N suffix) | Yes (N suffix) | Yes (N suffix) | No (non-N finish) | No (non-N finish) |
| Device Family | MAX II | MAX II - same | MAX II - same | MAX II - same | MAX II - same | MAX II - same | MAX II - same |
Key Differentiators
- Non-volatile instant-on configuration from on-chip flash (vs SRAM-based FPGAs (e.g. Cyclone, Spartan))
- Industrial temperature range in the same TQFP-100 footprint (vs EPM570GT100C5N (commercial temperature 0 to +85 C))
- Multi-volt I/O support on every pin (vs Single-voltage glue-logic ICs (74-series))
Design Notes
Decouple every VCCINT pin with a 0.1 µF X5R/X7R ceramic capacitor placed within 5 mm of the package pad, and bulk-decouple each VCCIO bank with a 4.7 µF to 10 µF ceramic or low-ESR tantalum capacitor. MAX II devices have separate VCCINT and VCCIO rails - do not tie them together if the I/O bank must operate at a different voltage than the core. Estimate: total quiescent current is typically 5-10 mA for a fully-utilized EPM570 design; dynamic current scales with toggle rate per the Quartus PowerPlay analyzer.
TQFP-100 has 0.5 mm pitch leads - use 0.20 mm trace/space design rules with via-in-pad or microvia escape routing for breakout. Place the JTAG header (TCK/TMS/TDI/TDO plus GND) at the board edge for production programming access. The exposed thermal pad on TQFP-100 is not present on MAX II; only the standard ground pins are used for thermal dissipation. Keep high-speed traces away from the JTAG signals to avoid coupling during in-system programming.
Group I/O pins by bank voltage on the schematic before pin assignment in Quartus - mixing 1.8 V and 3.3 V signals on the same bank is not allowed on MAX II. Use Quartus pin-planner to lock each I/O bank to a single VCCIO rail. Leave at least one GND pin per I/O bank to provide a low-impedance return path; the TQFP-100 package has GND on pins 11, 28, 50, and 85 - place decoupling capacitors adjacent to each.
Do not assume the EPM570T10015 is pin-compatible with newer MAX V or MAX 10 CPLDs - those families use different pinout maps even at the same TQFP-100 package. Always re-validate the pin assignment file when migrating between MAX II, MAX V, and MAX 10. Also note that the 'T' suffix in EPM570T10015 indicates TQFP-100, not 'turbo' or 'high-speed'; the speed-grade number follows the package code (e.g. '15' = 15 ns tPD).
Compliance Information
RoHS/REACH status not confirmed in the verified web data; lead-free ('N' suffix) variants EPM570GT100I5N, EPM570GT100C5N, EPM570F100I5N, EPM570F100C5N are explicitly lead-free per Altera/Intel marking convention, while EPM570GT100C5 and EPM570GT100I5 are non-N (Pb-containing) finishes. AEC-Q100 not applicable to CPLDs.
