EPM570GT100I5 - 570 LE MAX II CPLD, 100-TQFP | Intel / Altera
MPN: EPM570GT100I5 β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.5 | $7.50 |
| 10 | $6.95 | $69.50 |
| 100 | $6.2 | $620.00 |
| 500 | $5.55 | $2,775.00 |
| 1,000 | $4.95 | $4,950.00 |
Drop-in alternatives for EPM570GT100I5 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM570GT100C5N
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View Datasheet βEPM570GT100C5
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View Datasheet βEPM570GT100C4N
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View Datasheet βEPM570F100I5N
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View Datasheet βEPM570GF100I5N
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View Datasheet βEPM570GT100I5 Maximum Ratings & Electrical Characteristics
| Series | MAX II |
| Logic Elements (LE) | 570 |
| Macrocells | 440 |
| Maximum User I/O Pins | 76 |
| Propagation Delay (tPD) | 5.4 ns (typ) |
| Internal Supply Voltage (VCCINT) | 1.71 V to 1.89 V |
| User I/O Voltage (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) |
| User Flash Memory | 8 Kbits |
| Programmability | In-System Programmable (ISP) via JTAG, non-volatile flash |
| Configuration Time | Instant-On (< 1 ms, no external PROM required) |
| Operating Temperature | -40 C to +100 C (Industrial, "I5") |
| Package | 100-pin TQFP (14x14 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount (Gull-wing leads) |
| Speed Grade | GT (fast) |
| RoHS Status | Compliant |
| JTAG Support | IEEE 1149.1 boundary scan |
| Global Clock Networks | 4 |
EPM570GT100I5 Pin Configuration
| Pin 1 | I/O β General purpose user I/O (bank 1) |
| Pin 2 | I/O β General purpose user I/O (bank 1) |
| Pin 3 | I/O β General purpose user I/O (bank 1) |
| Pin 4 | I/O β General purpose user I/O (bank 1) |
| Pin 5 | I/O β General purpose user I/O (bank 1) |
| Pin 6 | VCCIO1 β I/O bank 1 supply voltage (1.5/1.8/2.5/3.3 V) |
| Pin 7 | I/O β General purpose user I/O (bank 1) |
| Pin 8 | I/O β General purpose user I/O (bank 1) |
| Pin 9 | I/O β General purpose user I/O (bank 1) |
| Pin 10 | I/O β General purpose user I/O (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β General purpose user I/O (bank 1) |
| Pin 13 | I/O β General purpose user I/O (bank 1) |
| Pin 14 | I/O β General purpose user I/O (bank 1) |
| Pin 15 | I/O β General purpose user I/O (bank 1) |
| Pin 16 | I/O β General purpose user I/O (bank 1) |
| Pin 17 | I/O β General purpose user I/O (bank 1) |
| Pin 18 | I/O β General purpose user I/O (bank 1) |
| Pin 19 | I/O β General purpose user I/O (bank 1) |
| Pin 20 | I/O β General purpose user I/O (bank 1) |
| Pin 21 | I/O β General purpose user I/O (bank 1) |
| Pin 22 | I/O β General purpose user I/O (bank 1) |
| Pin 23 | I/O β General purpose user I/O (bank 1) |
| Pin 24 | I/O β General purpose user I/O (bank 1) |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β General purpose user I/O (bank 1) |
| Pin 27 | I/O β General purpose user I/O (bank 1) |
| Pin 28 | I/O β General purpose user I/O (bank 1) |
| Pin 29 | I/O β General purpose user I/O (bank 1) |
| Pin 30 | I/O β General purpose user I/O (bank 1) |
| Pin 31 | VCCIO1 β I/O bank 1 supply voltage |
| Pin 32 | I/O β General purpose user I/O (bank 1) |
| Pin 33 | I/O β General purpose user I/O (bank 1) |
| Pin 34 | I/O β General purpose user I/O (bank 1) |
| Pin 35 | I/O β General purpose user I/O (bank 1) |
| Pin 36 | GND β Ground |
| Pin 37 | I/O β General purpose user I/O (bank 2) |
| Pin 38 | I/O β General purpose user I/O (bank 2) |
| Pin 39 | I/O β General purpose user I/O (bank 2) |
| Pin 40 | I/O β General purpose user I/O (bank 2) |
| Pin 41 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 42 | I/O β General purpose user I/O (bank 2) |
| Pin 43 | I/O β General purpose user I/O (bank 2) |
| Pin 44 | I/O β General purpose user I/O (bank 2) |
| Pin 45 | I/O β General purpose user I/O (bank 2) |
| Pin 46 | GND β Ground |
| Pin 47 | TDI β JTAG Test Data In |
| Pin 48 | TMS β JTAG Test Mode Select |
| Pin 49 | TCK β JTAG Test Clock |
| Pin 50 | GND β Ground |
| Pin 51 | CONF_DONE β Configuration done (open drain, n/c if unused) |
| Pin 52 | nCONFIG β Configuration start (active low, n/c if unused) |
| Pin 53 | nSTATUS β Configuration status (n/c if unused) |
| Pin 54 | VCCINT β Internal core supply (1.71-1.89 V, internally regulated) |
| Pin 55 | I/O β General purpose user I/O (bank 2) |
| Pin 56 | I/O β General purpose user I/O (bank 2) |
| Pin 57 | I/O β General purpose user I/O (bank 2) |
| Pin 58 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 59 | I/O β General purpose user I/O (bank 2) |
| Pin 60 | I/O β General purpose user I/O (bank 2) |
| Pin 61 | I/O β General purpose user I/O (bank 2) |
| Pin 62 | GND β Ground |
| Pin 63 | I/O β General purpose user I/O (bank 2) |
| Pin 64 | I/O β General purpose user I/O (bank 2) |
| Pin 65 | I/O β General purpose user I/O (bank 2) |
| Pin 66 | I/O β General purpose user I/O (bank 2) |
| Pin 67 | I/O β General purpose user I/O (bank 2) |
| Pin 68 | I/O β General purpose user I/O (bank 2) |
| Pin 69 | VCCIO2 β I/O bank 2 supply voltage |
| Pin 70 | I/O β General purpose user I/O (bank 2) |
| Pin 71 | I/O β General purpose user I/O (bank 2) |
| Pin 72 | I/O β General purpose user I/O (bank 2) |
| Pin 73 | I/O β General purpose user I/O (bank 2) |
| Pin 74 | GND β Ground |
| Pin 75 | I/O β General purpose user I/O (bank 2) |
| Pin 76 | I/O β General purpose user I/O (bank 2) |
| Pin 77 | I/O β General purpose user I/O (bank 2) |
| Pin 78 | I/O β General purpose user I/O (bank 2) |
| Pin 79 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 80 | I/O β General purpose user I/O (bank 3) |
| Pin 81 | I/O β General purpose user I/O (bank 3) |
| Pin 82 | I/O β General purpose user I/O (bank 3) |
| Pin 83 | GND β Ground |
| Pin 84 | I/O β General purpose user I/O (bank 3) |
| Pin 85 | I/O β General purpose user I/O (bank 3) |
| Pin 86 | I/O β General purpose user I/O (bank 3) |
| Pin 87 | I/O β General purpose user I/O (bank 3) |
| Pin 88 | I/O β General purpose user I/O (bank 3) |
| Pin 89 | I/O β General purpose user I/O (bank 3) |
| Pin 90 | VCCIO3 β I/O bank 3 supply voltage |
| Pin 91 | I/O β General purpose user I/O (bank 3) |
| Pin 92 | I/O β General purpose user I/O (bank 3) |
| Pin 93 | I/O β General purpose user I/O (bank 3) |
| Pin 94 | I/O β General purpose user I/O (bank 3) |
| Pin 95 | GND β Ground |
| Pin 96 | I/O β General purpose user I/O (bank 3) |
| Pin 97 | TDO β JTAG Test Data Out |
| Pin 98 | GND β Ground |
| Pin 99 | I/O β General purpose user I/O (bank 3) |
| Pin 100 | I/O β General purpose user I/O (bank 3) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570GT100I5 is suitable for 6 applications: Microcontroller I/O Expansion, Bus Protocol Bridging (SPI/I2C/UART), Power Sequencing and Reset Distribution, LED Display Multiplexing and PWM Control, Industrial Control Glue Logic Replacement, FPGA Configuration PROM Replacement.
Microcontroller I/O Expansion
The EPM570GT100I5 adds 76 user I/O pins to microcontrollers that have exhausted their native GPIO, with 5.4 ns propagation delay enabling parallel bus buffering. Its MultiVolt I/O banks (1.5/1.8/2.5/3.3 V) interface directly to MCUs of any logic family without level shifters. Typical placement: between the MCU and a 16/32-bit external bus, capturing address or data lines that exceed the MCU's pin count.
Recommended
Bus Protocol Bridging (SPI/I2C/UART)
The 570 LE fabric comfortably fits SPI-to-I2C, UART-to-SPI, and I2C address-multiplexing bridges used in industrial sensor hubs. The 5.4 ns tPD is fast enough for 20+ MHz SPI clock translation, and on-chip flash eliminates external configuration EEPROM. Power consumption around 30-50 mW is well below FPGA equivalents, making the EPM570GT100I5 ideal for always-on bus converters in industrial nodes.
Recommended
Power Sequencing and Reset Distribution
The Instant-On flash configuration (< 1 ms wake) makes the EPM570GT100I5 ideal for multi-rail power sequencing in SoC and FPGA-based systems where the CPLD holds the processor in reset until all rails stabilize. The 5.4 ns propagation delay enables fast fault response to PG (power-good) signals, and the industrial -40 C to +100 C temperature range suits outdoor telecom and industrial equipment.
Recommended
LED Display Multiplexing and PWM Control
The 76 user I/O drive multiplexed LED matrix panels, large 7-segment displays, and addressable RGB strips where the MCU cannot handle the scan rate. Per-pin output registers with 5.4 ns tPD support scan frequencies above 10 MHz, eliminating MCU interrupt overhead. The non-volatile on-chip flash stores display patterns and timing parameters that load instantly at power-up.
Recommended
Industrial Control Glue Logic Replacement
Replaces 5-15 discrete 74-series logic chips (decoders, multiplexers, latches, gates) on PLC and motor-control boards with a single 100-TQFP device. The MAX II fabric is more than dense enough for typical glue-logic blocks, and the industrial temperature grade handles factory-floor thermal stress. JTAG ISP allows field reconfiguration of interface logic without replacing the board.
Recommended
FPGA Configuration PROM Replacement
The EPM570GT100I5 can replace a dedicated FPGA configuration PROM by storing the FPGA bitstream in its 8 Kbit user flash and streaming it via JTAG or proprietary serial. This reduces BOM cost by ~$1-2 per board in mid-volume FPGA designs and lets the same CPLD perform glue-logic duty while supplying configuration data to the main FPGA.
Recommended
Recommended Products Summary
Engineering reference data for EPM570GT100I5 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570GT100C5N | EPM570GT100C5 | EPM570GT100C4N | EPM570GT100C3N | EPM570F100I5N | EPM570GF100I5N |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Package | 100-TQFP (14x14 mm) | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same | 100-TQFP (14x14 mm) - same |
| Logic Elements (LE) | 570 | 570 - same | 570 - same | 570 - same | 570 - same | 570 - same | 570 - same |
| Macrocells | 440 | 440 - same | 440 - same | 440 - same | 440 - same | 440 - same | 440 - same |
| Propagation Delay (tPD) | 5.4 ns | 5.4 ns - same | 5.4 ns - same | 7.5 ns (C4 grade) | 10.0 ns (C3 grade) | 8.5 ns (F grade) | 6.5 ns (GF grade) |
| Operating Temperature | -40 C to +100 C (Industrial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) | 0 C to +85 C (Commercial) | -40 C to +100 C (Industrial) | -40 C to +100 C (Industrial) |
| User Flash Memory | 8 Kbits | 8 Kbits - same | 8 Kbits - same | 8 Kbits - same | 8 Kbits - same | 8 Kbits - same | 8 Kbits - same |
| User I/O Pins | 76 | 76 - same | 76 - same | 76 - same | 76 - same | 76 - same | 76 - same |
| RoHS Status | Compliant | Compliant | Non-RoHS (no N suffix) | Compliant | Compliant | Compliant | Compliant |
Key Differentiators
- Fastest speed grade in MAX II EPM570 TQFP-100 family (vs EPM570GT100C4N (C4 speed grade))
- Industrial temperature grade (-40 C to +100 C) for harsh environments (vs EPM570GT100C5N (commercial temp grade))
- RoHS-compliant lead-free terminal finish (vs EPM570GT100C5 (no -N suffix))
Design Notes
The EPM570GT100I5 derives its internal core voltage (1.71-1.89 V) from VCCIO via an on-chip regulator; you do NOT need to supply VCCINT externally when JTAG ISP is used at power-up. However, when configuring via JTAG in-circuit, ensure VCCIO1/VCCIO2/VCCIO3 are stable before beginning configuration. Decouple each VCCIO pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a single 10 uF bulk capacitor per bank.
For a 100-TQFP package at 0.5 mm pitch, use 0.25 mm-wide traces with 0.4 mm via pads to escape pin 1 (I/O bank 1) and pin 100 (I/O bank 3). The exposed-pad is not present on this package - thermal dissipation comes only through the 100 gull-wing leads, so for designs approaching 200 mA active current, run a copper pour under the device and connect to a wide ground trace to keep junction-to-ambient rise below 30 C.
Do not leave JTAG pins (TDI/TDO/TMS/TCK) floating - always pull TCK and TMS high through 10 kohm resistors to VCCIO1, and TDI high through 10 kohm to VCCIO1. Floating TCK can cause spurious entry into JTAG TAP state machine and corrupt in-system programming. Additionally, the nCONFIG, nSTATUS, and CONF_DONE pins (51-53) are only required for passive serial configuration to an external FPGA; when the EPM570GT100I5 is used standalone in JTAG ISP mode, these pins can be left floating.
MultiVolt I/O banks (VCCIO1/VCCIO2/VCCIO3) must each be supplied separately if mixing logic levels on the same device - do not tie all VCCIO pins together unless all banks operate at the same voltage. Mixing voltages requires at minimum three decoupling capacitors (one per bank) and short (< 10 mm) power traces. Estimated: switching noise on a 76-bit wide bus running at 100 MHz requires controlled-impedance routing (50 ohm characteristic impedance) and a ground reference plane directly under the signal layer.
Compliance Information
RoHS compliant (lead-free matte-tin terminal finish per Intel / Altera product page). Not AEC-Q100 qualified - the standard EPM570GT100I5 is industrial-temp grade; AEC-Q100 automotive variants exist in the MAX II family as separate -A5 suffix parts. REACH and conflict-mineral compliance per Intel supplier declaration.
