EPM7096LC68-15 vs EPM7096QC100-10 Comparison

Detailed side-by-side comparison of EPM7096LC68-15 by Altera and EPM7096QC100-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7096LC68-15 EPM7096QC100-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Nrnd Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.20 $7.10
Family MAX 7000 MAX 7000
Macrocells 96 96
Logic Array Blocks (LABs) 4 β€”
User I/O Pins 52 76
Propagation Delay (tPD) 15 ns 10 ns
Supply Voltage (VCCINT/VCCIO) 4.75 V to 5.25 V (5 V nominal) β€”
Programmable Technology EEPROM (second-generation MAX architecture) β€”
In-System Programming Yes (IEEE 1149.1 JTAG) β€”
Logic Gates (typical) 1800 gates β€”
Memory Bits Non-volatile configuration, 100 erase/program cycles per macrocell β€”
Package PLCC-68 (LC68) 100-pin PQFP (R-PQFP-G100, 20Γ—14 mm, 0.65 mm pitch)
Mounting Type Surface Mount (PLCC socket compatible) Surface Mount
Operating Temperature 0C to +70C (commercial) 0 Β°C to +70 Β°C (commercial)
Lead-Free / RoHS Compliant per Altera product page β€”
Programming Tool Support Altera MAX+PLUS II, Quartus II; ByteBlaster / ByteBlasterMV β€”
Logic Array Blocks β€” 4
Maximum Operating Frequency β€” 100 MHz
Supply Voltage (VCC) β€” 4.75 V to 5.25 V
Technology β€” EEPROM-based CMOS
Programming Interface β€” ByteBlaster / parallel (JTAG ISP on MAX 7000S variants)
Boundary Scan β€” IEEE Std. 1149.1 (JTAG) on MAX 7000S
PCI Compliance β€” Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade)
RoHS Status β€” [DATA_NEEDED: RoHS compliance status]

Datasheets & Resources

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