EPM7096LC84-10 - 96-Macrocell MAX 7000 CPLD, 10ns, 84-PLCC | Intel
MPN: EPM7096LC84-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $9.8 | $9.80 |
| 10 | $8.65 | $86.50 |
| 100 | $7.4 | $740.00 |
| 500 | $6.2 | $3,100.00 |
| 1,000 | $5.1 | $5,100.00 |
Drop-in alternatives for EPM7096LC84-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7096LC84-12
β Drop-Inπ Reference alternative (not in catalog)
EPM7096LC84-15
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM7128ELC84-15
β Drop-Inπ Reference alternative (not in catalog)
EPM7128SLC84-10N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128ELC84-10
β Drop-Inπ Reference alternative (not in catalog)
EPM7064LC84-10
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM7096LC84-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 96 |
| Logic Array Blocks (LABs) | 4 |
| Maximum User I/O Pins | 36 |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) |
| Package | 84-PLCC (J-Lead) |
| Process Technology | EEPROM-based, 5.0 V low-power CMOS (L) |
| Supply Voltage (VCC) | 5.0 V nominal (4.75 V - 5.25 V) |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG |
| MultiVolt I/O | 2.5 V / 3.3 V / 5.0 V mixed-voltage interface |
| Operating Temperature Range | 0C to +70C (Commercial, 'C') |
| Configuration Memory | Non-volatile EEPROM (instant-on) |
| Programmable Interconnect | PIA (Programmable Interconnect Array) |
| Mounting Type | Surface Mount (PLCC socket or SMT) |
EPM7096LC84-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (macrocell-driven bidirectional) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | GND β Ground |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | TDI β JTAG Test Data In |
| Pin 44 | TMS β JTAG Test Mode Select |
| Pin 45 | TCK β JTAG Test Clock |
| Pin 46 | TDO β JTAG Test Data Out |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | GND β Ground |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | GND β Ground |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | GND β Ground |
| Pin 84 | VCC β +5 V supply |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7096LC84-10 is suitable for 6 applications: 5V Microcontroller Glue Logic, Bus Interface & Address Decoding, Industrial Control & State Machines, Legacy Peripheral Control (Printers / Scanners), JTAG Boundary-Scan Test Access, Replacement of Discrete TTL Gate Arrays.
5V Microcontroller Glue Logic
The EPM7096LC84-10's 96 macrocells and 36 I/O pins make it well suited to replace chains of 74LS/74HC glue logic around a 5-V microcontroller such as the Intel 8051, Motorola 68HC11, or Microchip PIC. With a 10 ns tPD, the device can decode address lines and generate chip-select strobes at system clock rates up to 50 MHz without timing-margin concerns. Its 5.0-V MultiVolt I/O ports can directly drive 3.3-V peripherals through series resistors or level translators, simplifying mixed-voltage board designs. Designers should reserve JTAG pins TDI/TMS/TCK/TDO for boundary-scan access during board test, allowing in-system firmware updates without removing the chip.
Recommended
Bus Interface & Address Decoding
The EPM7096LC84-10 is widely deployed in ISA, PCI, and proprietary backplane interfaces where address decoding must be deterministic across temperature. Its product-term-based logic array and shared PIA deliver fixed tPD independent of which LAB a signal enters, which is critical for chip-select timing in DMA-bus architectures. The 36 user I/O pins are sufficient to decode 24-bit address buses plus 8-chip-select outputs. The 5.0-V VCC rail aligns with legacy 5-V host bus signaling, eliminating level-translation circuitry. For modern 3.3-V-only systems, the same die is offered in 3.3-V variants (EPM7096S) that retain pinout compatibility.
Recommended
Industrial Control & State Machines
The non-volatile EEPROM configuration of the EPM7096LC84-10 makes it ideal for industrial PLCs and motor-control boards that must boot into a known state without external boot PROMs. Each of the 96 macrocells can implement D, T, JK, or SR flip-flops, supporting large Moore or Mealy state machines for sequencing conveyor belts, solenoid drivers, or stepper-motor pulse generators. The 0C to +70C commercial operating range suits most factory-floor enclosures; industrial-temperature variants (EPM7096LI84-10) extend coverage to -40C to +85C. The JTAG ISP interface lets technicians re-load ladder-logic-equivalent state machines through the board's test connector without removing the chip.
Recommended
Legacy Peripheral Control (Printers / Scanners)
Print engines, scanner stepper motors, and legacy USB-to-parallel bridges often require parallel-control glue logic that the EPM7096LC84-10 implements in a single chip. Its 36 I/O pins can drive head-position encoders, paper-feed stepper coils, and LED status banks simultaneously, while the macrocell array handles stepper pulse-train generation and PWM-like dimming control. The instant-on EEPROM configuration means the printer is operational within microseconds of power-up, satisfying warm-boot timing requirements. Replacement of original 74LS glue logic with one CPLD reduces PCB area and improves noise immunity through fewer high-speed signal traces.
Recommended
JTAG Boundary-Scan Test Access
The built-in IEEE 1149.1 JTAG interface of the EPM7096LC84-10 lets the device itself act as a boundary-scan master or slave in board-level test fixtures. By assigning all 36 user I/O pins to JTAG boundary-scan registers, the CPLD can chain test access to adjacent BGA and QFP devices that lack visible test points. The 10 ns tPD does not limit boundary-scan capture-clock rates since scan operations occur at the JTAG TCK frequency (typically 10-100 MHz), independent of the CPLD's functional tPD. Combined with the ISP capability, the same JTAG port re-loads firmware and runs structural board tests - a true single-test-access design.
Recommended
Replacement of Discrete TTL Gate Arrays
Designers often face legacy boards populated with 30+ discrete 74LS/74HC/74F packages implementing address decoding, bus arbitration, and interrupt prioritization. The EPM7096LC84-10, with 96 macrocells, can absorb all of these functions into a single 84-PLCC device, reducing PCB area, lowering power consumption through CMOS design, and improving reliability by removing solder joints. The MultiVolt I/O pins let the same CPLD interface to 5-V and 3.3-V logic islands on the board, eliminating the cross-voltage glue that often accompanies mixed-logic redesigns. Migration to the same-die MAX II EPM570 is recommended only if board area constraints demand a smaller package.
Recommended
Recommended Products Summary
Engineering reference data for EPM7096LC84-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7096LC84-12 | EPM7096LC84-15 | EPM7128ELC84-15 | EPM7128SLC84-10N | EPM7064LC84-10 |
|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same |
| Macrocells | 96 | 96 | 96 | 128 | 128 | 64 |
| Propagation Delay (tPD) | 10 ns | 12 ns | 15 ns | 15 ns | 10 ns | 10 ns |
| Logic Array Blocks | 4 | 4 | 4 | 8 | 8 | 4 |
| Maximum User I/O | 36 | 36 | 36 | 36 | 36 | 36 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| In-System Programmability | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Pin-to-Pin Drop-In | Reference | Yes | Yes | Yes | Yes | Yes |
Key Differentiators
- Higher macrocell density at same speed grade (vs EPM7064LC84-10)
- Faster speed grade than EPM7128ELC84-15 (vs EPM7128ELC84-15)
- 5-V native supply matches legacy 5-V systems (vs MAX II EPM570 (modern alternative))
Design Notes
Estimated: At a 5.0 V VCC with all 36 I/O pins toggling at 25 MHz into 50 pF loads, the EPM7096LC84-10 draws approximately 200-300 mA. Place one 0.1 uF ceramic decoupling capacitor within 5 mm of each VCC pin (pins 84, plus internal supply pins) and a 10 uF bulk tantalum or ceramic capacitor at the board's power-entry point. The four GND pins (11, 23, 41, 55, 69, 83) must all be tied to a low-impedance ground plane; missing even one GND connection can cause intermittent JTAG failures under load.
Route the four JTAG signals (TDI pin 43, TMS pin 44, TCK pin 45, TDO pin 46) as a short, impedance-controlled cluster with a guard ground on either side. Keep JTAG traces under 50 mm to avoid reflection-induced programming failures. The TCK line in particular should be length-matched to within 5 mm of any buffered JTAG node downstream. If the board uses a 10-pin or 14-pin JTAG header, add a 10 kohm pull-up on TMS and TDI per IEEE 1149.1 spec to keep the TAP controller in a benign state during board reset.
Do not assume the -10, -12, and -15 speed-grade variants are interchangeable without re-running timing closure. The 2 ns and 5 ns tPD differences can violate setup/hold margins in synchronous designs clocked above 33 MHz. Pinout is identical across speed grades, so PCB fabrication is unaffected - only the device marking changes. Also note that the 'L' suffix denotes the 5-V low-power CMOS process; the 3.3-V 'S' variants (EPM7096SLC84-10) require VCC of 3.3 V and are NOT pin-compatible at the supply pin - mixing them on the same board will damage the 'L' part.
Compliance Information
RoHS/lead-free status not stated in verified web data for this specific MPN. The MAX 7000 family is generally lead-bearing per legacy Altera process; the lead-free variant carries a '-N' suffix in the part number (e.g., EPM7096LC84-10N). Verify against the device marking or manufacturer PCN for production designs.
