EPM7096QC100-10 vs EPM7096LC84-15 Comparison
Detailed side-by-side comparison of EPM7096QC100-10 by Altera and EPM7096LC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7096QC100-10 - 96-Macrocell MAX 7000 CPLD, 10ns, PQFP-100 | Altera
EPM7096QC100-10 Obsolete
Specification Comparison
| Parameter | EPM7096QC100-10 | EPM7096LC84-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 7000 | MAX 7000 |
| Macrocells | 96 | — |
| Logic Array Blocks | 4 | — |
| User I/O Pins | 76 | 68 (36 per LAB, [DATA_NEEDED: exact LAB-level split]) |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Operating Frequency | 100 MHz | 76.9 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Technology | EEPROM-based CMOS | — |
| Programming Interface | ByteBlaster / parallel (JTAG ISP on MAX 7000S variants) | IEEE Std. 1149.1 JTAG |
| Boundary Scan | IEEE Std. 1149.1 (JTAG) on MAX 7000S | — |
| PCI Compliance | Yes (PCI SIG Local Bus Specification Rev. 2.2 at -10 speed grade) | — |
| Operating Temperature | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| Package | 100-pin PQFP (R-PQFP-G100, 20×14 mm, 0.65 mm pitch) | — |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Series | — | MAX 7000 (second-generation MAX architecture) |
| Macro Cells | — | 96 |
| Logic Array Blocks (LABs) | — | 4 |
| Usable Gates | — | 1,800 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Programmable Type | — | EE PLD (in-system programmable via JTAG) |
| Package / Case | — | 84-PLCC (J-Lead) |
| Supplier Device Package | — | 84-PLCC (29.31 x 29.31 mm) |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| Erase/Program Endurance | — | [DATA_NEEDED: erase/program cycle count] |