EPM7128SQC100-7N vs EPM7128AETC100-7N Comparison
Detailed side-by-side comparison of EPM7128SQC100-7N by Intel and EPM7128AETC100-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N Obsolete
Specification Comparison
| Parameter | EPM7128SQC100-7N | EPM7128AETC100-7N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.10 | $31.80 |
| Family | MAX 7000S | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD - Complex Programmable Logic Device |
| Program Memory Type | EEPROM | β |
| Number of Macrocells | 128 | β |
| Number of Logic Array Blocks | 8 | β |
| Number of Global Clocks | 2 | β |
| Product Terms per Macrocell | 32 | β |
| Usable Gates | 2,500 | 2,500 |
| System Gates | 5,000 (max) | β |
| Maximum User I/Os | 84 | β |
| Pin-to-Pin Delay (tPD) | 7.5 ns | β |
| Counter Speed | 175.4 MHz | β |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| Operating Voltage (Core) | 5.0 V | β |
| I/O Standard Support | multiVolt (2.5V, 3.3V, 5.0V) | β |
| Package | 100-pin PQFP (QFP-100) | 100-TQFP |
| Operating Temperature | 0C to +70C (commercial) | 0 C to +70 C (Commercial) |
| RoHS Status | Compliant (lead-free 'N' suffix) | [DATA_NEEDED: RoHS status] |
| Process Technology | 0.30 Β΅m CMOS EEPROM | 0.30 Β΅m EEPROM CMOS |
| Security Bit | Programmable (one per device) | β |
| Macro Cells | β | 128 |
| Logic Array Blocks (LABs) | β | 4 |
| User I/Os | β | 84 |
| Propagation Delay (tpd) | β | 7.5 ns |
| Counter Frequency (max) | β | 129.9 MHz |
| Internal Frequency (max) | β | 250 MHz |
| Core Supply Voltage | β | 3.3 V |
| Logic Family | β | CMOS |
| Pin Count | β | 100 |
| Mounting Type | β | Surface Mount |
| Programming Interface | β | JTAG (IEEE 1149.1) / ISP |