EPM7128STC100-15N vs EPM7128SQC100-15 Comparison
Detailed side-by-side comparison of EPM7128STC100-15N by Intel and EPM7128SQC100-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteAltera
EPM7128SQC100-15 - MAX 7000 CPLD 128MC 15ns 5V | Altera/Intel
EPM7128SQC100-15 β Last Time BuySpecification Comparison
| Parameter | EPM7128STC100-15N | EPM7128SQC100-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.20 | $8.20 |
| Product Type | CPLD (Complex Programmable Logic Device) | β |
| Family | MAX 7000S | MAX 7000 |
| Usable Gates | 2,500 | β |
| Macro Cells | 128 | β |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | 4 (16 macrocells each) |
| Maximum User I/O | 84 | β |
| Pin-to-Pin Logic Delay (tPD) | 15 ns (-15 speed grade) | β |
| Maximum Internal Frequency | 76.9 MHz | β |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | β |
| Supply Voltage (VCCIO) | 3.3 V or 5 V (per bank) | β |
| Technology | CMOS EEPROM, in-system programmable | β |
| Package | 100-pin TQFP | 100-pin PQFP (Plastic Quad Flat Pack) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (Commercial) |
| JTAG (IEEE 1149.1) | Yes - in-system programming | β |
| Output Options | Totem-pole or open-drain (per pin) | β |
| Dedicated Inputs | 4 global inputs | β |
| RoHS Status | Non-RoHS (legacy SnPb finish typical) | Non-compliant (SnPb lead finish - legacy PQFP) |
| Lifecycle Status | Obsolete (PDN effective 2017-06-01) | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macrocells | β | 128 |
| User I/Os | β | 84 |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Maximum Frequency (fMAX) | β | [DATA_NEEDED: fMAX value] |
| Typical Gate Count | β | 2,500 gates |
| Supply Voltage (VCCINT) | β | 5 V (5% tolerance) |
| Programming Technology | β | EEPROM (in-system programmable via JTAG) |
| JTAG Interface | β | IEEE Std. 1149.1 compliant |
| Mounting Type | β | Surface Mount |
| MSL Level | β | 3 (168 hours) |