EPM7128STC100-6N vs EPM7128STC100-15N Comparison

Detailed side-by-side comparison of EPM7128STC100-6N by Altera and EPM7128STC100-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7128STC100-6N EPM7128STC100-15N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 7000S MAX 7000S
Usable Gates 2,500 2,500
Macro Cells 128 128
User I/Os 84 —
Logic Family CMOS —
Number of Pins 100 —
Package Type TQFP-100 —
Maximum Internal Frequency 147.1 MHz 76.9 MHz
Internal Counter Frequency 250 MHz —
Propagation Delay (tPD) 6 ns —
Pin-to-Pin Delay 4.5 ns —
Supply Voltage (VCCIO) 5 V 3.3 V or 5 V (per bank)
Process Technology CMOS EEPROM —
Programmability In-System Programmable (ISP) via JTAG —
JTAG Support IEEE 1149.1 Boundary Scan —
Operating Temperature 0C to +70C (Commercial) 0C to +70C (commercial)
Mounting Type Surface Mount —
RoHS Status Non-Compliant (lead-bearing package) Non-RoHS (legacy SnPb finish typical)
Product Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 8 (16 macro cells each)
Maximum User I/O — 84
Pin-to-Pin Logic Delay (tPD) — 15 ns (-15 speed grade)
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Technology — CMOS EEPROM, in-system programmable
Package — 100-pin TQFP
JTAG (IEEE 1149.1) — Yes - in-system programming
Output Options — Totem-pole or open-drain (per pin)
Dedicated Inputs — 4 global inputs
Lifecycle Status — Obsolete (PDN effective 2017-06-01)

Datasheets & Resources

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