EPM7128STC100-6N vs EPM7128STC100-15N 비교
다음의 상세 나란히 비교: EPM7128STC100-6N 제조: Altera 및 EPM7128STC100-15N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteIntel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N Obsolete사양 비교
| 파라미터 | EPM7128STC100-6N | EPM7128STC100-15N |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $10.50 | $9.20 |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | 128 |
| User I/Os | 84 | — |
| Logic Family | CMOS | — |
| 핀 수 | 100 | — |
| Package Type | TQFP-100 | — |
| Maximum Internal Frequency | 147.1 MHz | 76.9 MHz |
| Internal Counter Frequency | 250 MHz | — |
| Propagation Delay (tPD) | 6 ns | — |
| Pin-to-Pin Delay | 4.5 ns | — |
| Supply Voltage (VCCIO) | 5 V | 3.3 V or 5 V (per bank) |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| 동작 온도 | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| 실장 유형 | Surface Mount | — |
| RoHS 상태 | Non-Compliant (lead-bearing package) | Non-RoHS (legacy SnPb finish typical) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns (-15 speed grade) |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Technology | — | CMOS EEPROM, in-system programmable |
| 패키지 | — | 100-pin TQFP |
| JTAG (IEEE 1149.1) | — | Yes - in-system programming |
| Output Options | — | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | — | 4 global inputs |
| 수명 주기 상태 | — | Obsolete (PDN effective 2017-06-01) |