EPM7128STC100-6N vs EPM7128STC100-15N Vergleich
Detaillierter Direktvergleich von EPM7128STC100-6N von Altera und EPM7128STC100-15N von Intel. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Altera
EPM7128STC100-6N - MAX 7000S 128-Macro-Cell CPLD | Altera | TQFP-100
EPM7128STC100-6N ObsoleteIntel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteSpezifikationsvergleich
| Parameter | EPM7128STC100-6N | EPM7128STC100-15N |
|---|---|---|
| Marke | Altera | Intel |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $10,50 | $9,20 |
| Family | MAX 7000S | MAX 7000S |
| Usable Gates | 2,500 | 2,500 |
| Macro Cells | 128 | 128 |
| User I/Os | 84 | — |
| Logic Family | CMOS | — |
| Anzahl der Pins | 100 | — |
| Package Type | TQFP-100 | — |
| Maximum Internal Frequency | 147.1 MHz | 76.9 MHz |
| Internal Counter Frequency | 250 MHz | — |
| Propagation Delay (tPD) | 6 ns | — |
| Pin-to-Pin Delay | 4.5 ns | — |
| Supply Voltage (VCCIO) | 5 V | 3.3 V or 5 V (per bank) |
| Process Technology | CMOS EEPROM | — |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Betriebstemperatur | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Montageart | Surface Mount | — |
| RoHS-Status | Non-Compliant (lead-bearing package) | Non-RoHS (legacy SnPb finish typical) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns (-15 speed grade) |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Technology | — | CMOS EEPROM, in-system programmable |
| Gehäuse | — | 100-pin TQFP |
| JTAG (IEEE 1149.1) | — | Yes - in-system programming |
| Output Options | — | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | — | 4 global inputs |
| Lebenszyklusstatus | — | Obsolete (PDN effective 2017-06-01) |