EPM7160STI100-10N vs EPM7160SLC84-10N Comparison
Detailed side-by-side comparison of EPM7160STI100-10N by Altera and EPM7160SLC84-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7160STI100-10N - MAX 7000S CPLD, 160 Macrocells, 100MHz, TQFP-100 | Intel/Altera
EPM7160STI100-10N β Last Time Buy
Specification Comparison
| Parameter | EPM7160STI100-10N | EPM7160SLC84-10N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last_time_buy | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.80 | $9.85 |
| Family | MAX 7000S | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | β |
| Macrocells | 160 | β |
| Usable Gates | 3200 | 3,200 gates |
| User I/Os | 84 (per Mouser listing; up to 104 per alternate datasheets) | β |
| Logic Blocks | 10 (LABs) | β |
| Propagation Delay (tPD) | 10 ns | β |
| Internal Frequency | 100 MHz | β |
| Supply Voltage VCC | 5.0 V (3.3 V or 5 V tolerant I/O via MAX 7000S multi-voltage ISP) | β |
| Programmable Technology | EEPROM (non-volatile) | β |
| In-System Programmability | Yes (JTAG/IEEE 1149.1, 5.0V ISP) | β |
| Operating Temperature | -40C to +85C (industrial, 'I' suffix) | β |
| Package Type | 100-pin TQFP (TQFP-100) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Lead-Free / RoHS | Yes (lead-free per 'I' industrial suffix) | Yes (-N suffix indicates lead-free) |
| Process Technology | CMOS, EEPROM-based | β |
| Logic Elements / Macrocells | β | 160 macrocells |
| Logic Array Blocks (LABs) | β | 4 |
| User I/O Pins | β | 64 (also reported as 60 or 36 depending on variant) |
| Pin-to-Pin Delay (tPD) | β | 10 ns |
| Counter Speed (fCNT) | β | up to 175.4 MHz |
| Maximum Operating Frequency | β | 100 MHz |
| Supply Voltage - Core (VCC) | β | 5.0 V |
| I/O Supply Voltage (VCCIO) | β | 3.3 V or 5.0 V |
| Configuration Memory | β | EEPROM (non-volatile) |
| In-System Programming | β | Yes, via IEEE Std. 1149.1 JTAG |
| Program / Erase Cycles | β | 100 minimum |
| Data Retention | β | 20 years minimum |
| Package | β | 84-pin PLCC (J-lead, surface mount) |
| Operating Temperature Grade | β | Commercial (0C to +70C) |