EPM7160STI100-10N - MAX 7000S CPLD, 160 Macrocells, 100MHz, TQFP-100 | Intel/Altera
MPN: EPM7160STI100-10N ⚠ Last Time Buy| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $13.5 | $13.50 |
| 10 | $11.9 | $119.00 |
| 100 | $10.2 | $1,020.00 |
| 500 | $8.85 | $4,425.00 |
| 1,000 | $7.8 | $7,800.00 |
Drop-in alternatives for EPM7160STI100-10N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM7160STI100-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 160 |
| Usable Gates | 3200 |
| User I/Os | 84 (per Mouser listing; up to 104 per alternate datasheets) |
| Logic Blocks | 10 (LABs) |
| Propagation Delay (tPD) | 10 ns |
| Internal Frequency | 100 MHz |
| Supply Voltage VCC | 5.0 V (3.3 V or 5 V tolerant I/O via MAX 7000S multi-voltage ISP) |
| Programmable Technology | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG/IEEE 1149.1, 5.0V ISP) |
| Operating Temperature | -40C to +85C (industrial, 'I' suffix) |
| Package Type | 100-pin TQFP (TQFP-100) |
| Mounting Type | Surface Mount |
| Lead-Free / RoHS | Yes (lead-free per 'I' industrial suffix) |
| Process Technology | CMOS, EEPROM-based |
EPM7160STI100-10N Pin Configuration
| Pin 1 | I/O — User I/O pin (per TQFP-100 pinout) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | I/O — User I/O pin |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | I/O — User I/O pin |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | VCC — 5.0V core supply |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | I/O — User I/O pin |
| Pin 26 | I/O — User I/O pin |
| Pin 27 | I/O — User I/O pin |
| Pin 28 | I/O — User I/O pin |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | I/O — User I/O pin |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | VCC — 5.0V core supply |
| Pin 42 | I/O — User I/O pin |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | I/O — User I/O pin |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | GND — Ground |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | I/O — User I/O pin |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | VCC — 5.0V core supply |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | I/O — User I/O pin |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | GND — Ground |
| Pin 72 | I/O — User I/O pin |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pin 77 | TMS — JTAG Test Mode Select |
| Pin 78 | TCK — JTAG Test Clock |
| Pin 79 | TDO — JTAG Test Data Out |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | INPUT/GCLK1 — Dedicated input / global clock |
| Pin 86 | INPUT/GCLK2 — Dedicated input / global clock |
| Pin 87 | INPUT/OE1 — Dedicated input / output enable |
| Pin 88 | INPUT/OE2 — Dedicated input / output enable |
| Pin 89 | INPUT/CLR — Dedicated input / clear |
| Pin 90 | I/O — User I/O pin |
| Pin 91 | I/O — User I/O pin |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | I/O — User I/O pin |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | I/O — User I/O pin |
| Pin 97 | I/O — User I/O pin |
| Pin 98 | I/O — User I/O pin |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7160STI100-10N is suitable for 6 applications: Microprocessor Address Decoding, Bus Interface Bridging, Legacy TTL/CMOS Glue Logic Replacement, Industrial Control I/O Expansion, Power Supply Sequencing & Control Logic, JTAG-Based Boundary-Scan Test Front-End.
Microprocessor Address Decoding
The EPM7160STI100-10N is widely used as a high-density address decoder for 5V microprocessor and microcontroller systems, replacing banks of 74LS138 / 74HC138 decoder ICs with a single programmable device. With 160 macrocells and 84 user I/Os in TQFP-100, the part can decode large memory and peripheral address spaces (e.g., 24-bit or 32-bit CPU buses) and generate chip-select signals with predictable 10 ns timing. The non-volatile EEPROM configuration means the decoder starts operating on power-up with no bootloader latency, critical for deterministic system bring-up. Designers benefit from JTAG-based in-system reprogrammability, allowing address-map changes without board rework.
Recommended
Bus Interface Bridging
The EPM7160STI100-10N bridges mismatched bus protocols in mixed-voltage 5V/3.3V systems, such as ISA-to-PCI, memory-to-ASIC, or legacy-MCU-to-modern-FPGA interfaces. The MAX 7000S family's multi-voltage ISP support (3.3V and 5V JTAG) and 5.0V VCC tolerance make it ideal for level-shifting and protocol-conversion glue logic. With 10 ns pin-to-pin delay and 100 MHz internal frequency, the device can sustain high-throughput data paths while still fitting in the TQFP-100 footprint used on thousands of legacy designs. In-system programming via the IEEE 1149.1 JTAG chain enables field firmware updates without removing the part from the board.
Recommended
Legacy TTL/CMOS Glue Logic Replacement
The EPM7160STI100-10N is frequently deployed to consolidate scattered 74-series TTL/CMOS glue logic - latches, multiplexers, parity generators, and shifters - into a single reprogrammable device. With 3,200 usable gates and 160 macrocells, one EPM7160S can replace 10-20 discrete MSI logic ICs, reducing PCB area, BOM cost, and supply-chain risk for obsolete 74LS/74F parts. The industrial -40C to +85C temperature range enables deployment in factory-automation and outdoor-instrumentation enclosures. Designers port existing discrete-logic schematics directly into Altera's MAX+PLUS II or Quartus II HDL, preserving proven timing behavior with the 10 ns tPD budget.
Recommended
Industrial Control I/O Expansion
The EPM7160STI100-10N provides deterministic, low-latency I/O expansion for PLCs, motor controllers, and industrial sensor interfaces where software-driven GPIO on a microcontroller is too slow or non-deterministic. With 84 user I/Os and 10 ns tPD, the CPLD can debounce mechanical switches, generate PWM outputs for motor-drive logic, and implement safety interlocks in parallel with the main CPU. The MAX 7000S family EEPROM-based non-volatile storage ensures the I/O map configuration survives power cycles without firmware reload. Industrial-temperature grade (-40C to +85C) and lead-free assembly suit harsh-environment deployments.
Recommended
Power Supply Sequencing & Control Logic
The EPM7160STI100-10N is used as a multi-rail power-supply sequencer in 5V industrial and telecom systems where FPGA, ASIC, and DSP cores require strict power-up and power-down ordering. Each of the 160 macrocells can implement a comparator-based rail-good detector combined with adjustable delay timers, generating precision enable signals for downstream DC-DC converters. The non-volatile EEPROM configuration means sequencing starts immediately at power-up without MCU intervention, and JTAG-based in-system programming allows last-minute sequencing changes during board bring-up. The TQFP-100 footprint integrates easily beneath or beside the power-tree ICs on standard 4-layer PCBs.
Recommended
JTAG-Based Boundary-Scan Test Front-End
The EPM7160STI100-10N supports IEEE 1149.1 JTAG boundary-scan and can be configured as a multi-device JTAG chain master or as a built-in self-test (BIST) controller on manufacturing test fixtures. With 84 user I/Os, the part can fan out TAP signals to multiple downstream clusters and aggregate pass/fail status. The 5.0V ISP-compatible JTAG interface simplifies in-system programming during board bring-up and field upgrades. Manufacturing-test engineers use the CPLD's deterministic 10 ns timing to capture at-speed functional vectors, reducing test-time versus software-driven boundary-scan alone.
Recommended
Recommended Products Summary
Engineering reference data for EPM7160STI100-10N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7160STC100-10N | EPM7160STI100-10 | EPM7160SQC160-10N |
|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 (referenced only - cross-package) |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Macrocells | 160 | 160 | 160 | 160 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 10 ns |
| Internal Frequency | 100 MHz | 100 MHz | 100 MHz | 100 MHz |
| Usable Gates | 3,200 | 3,200 | 3,200 | 3,200 |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Supply Voltage | 5.0V | 5.0V | 5.0V | 5.0V |
| Lifecycle Status | Last-time-buy | Last-time-buy | Obsolete | Last-time-buy |
Key Differentiators
- Industrial temperature grade with lead-free assembly in single part (vs EPM7160STC100-10N)
- Mid-density 160 macrocells with 84 I/Os in TQFP-100 (vs EPM7128STI100-10N)
- JTAG/IEEE 1149.1 ISP and boundary-scan (vs EPM7160SQC160-10N)
Design Notes
The EPM7160STI100-10N requires a monotonic 5.0V VCC ramp at power-up; voltage droop or non-monotonic rise can cause EEPROM configuration mis-reads. Decouple VCC with one 100 nF ceramic cap per VCC pin (4 caps on TQFP-100) plus a single 10 uF bulk tantalum or ceramic cap within 25 mm of the device. Hold all I/O inputs at valid logic levels until VCC stabilizes to avoid spurious EEPROM writes. Estimated quiescent current is approximately 10-30 mA standby plus macrocell-dependent dynamic current, so size upstream regulators with adequate headroom.
Route the JTAG chain (TDI/TDO/TMS/TCK) with 50-ohm controlled impedance and avoid stubs longer than 10 mm. Place the CPLD within 50 mm of the JTAG header to minimize reflections at TCK frequencies above 10 MHz. Provide a pull-up resistor (typically 4.7 kohm) on each JTAG signal if multiple devices share the chain, and add series ferrite beads if the board is in a noisy industrial environment. The TQFP-100 exposed pad (if present on the specific variant) should be soldered to a thermally grounded copper pour to reduce junction temperature.
Do not confuse the EPM7160STI100-10N with the EPM7160STC100-10N - the I-suffix indicates industrial temperature grade (-40C to +85C) while C-suffix is commercial (0C to +70C). Mixing them up in a BOM for outdoor industrial equipment will lead to field failures. The 'N' suffix indicates lead-free (Pb-free) assembly; non-N variants use lead-bearing solder and may not be RoHS-compliant. Confirm both 'I' and 'N' markers in the part number before placing volume orders, especially for end-customer applications requiring RoHS and industrial temperature concurrently.
Compliance Information
RoHS compliance inferred from 'N' suffix (lead-free) and 'I' industrial marking on datasheet. Halogen-free status and conflict-mineral declarations not stated in available distributor listings. AEC-Q100 not applicable - this is a programmable logic device, not an automotive-grade IC, but Altera MAX 7000S family has been used in industrial and some non-safety-critical automotive applications.
