EPM7160STI100-10N vs EPM7160SLC84-10N 비교

다음의 상세 나란히 비교: EPM7160STI100-10N 제조: Altera 및 EPM7160SLC84-10N 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM7160STI100-10N EPM7160SLC84-10N
브랜드 Altera Intel
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 최종 구매 Obsolete
재고 상태 In Stock In Stock
단가 (USD) $7.80 $9.85
Family MAX 7000S MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 160 —
Usable Gates 3200 3,200 gates
User I/Os 84 (per Mouser listing; up to 104 per alternate datasheets) —
Logic Blocks 10 (LABs) —
Propagation Delay (tPD) 10 ns —
Internal Frequency 100 MHz —
Supply Voltage VCC 5.0 V (3.3 V or 5 V tolerant I/O via MAX 7000S multi-voltage ISP) —
Programmable Technology EEPROM (non-volatile) —
In-System Programmability Yes (JTAG/IEEE 1149.1, 5.0V ISP) —
동작 온도 -40C to +85C (industrial, 'I' suffix) —
Package Type 100-pin TQFP (TQFP-100) —
실장 유형 Surface Mount Surface Mount
Lead-Free / RoHS Yes (lead-free per 'I' industrial suffix) Yes (-N suffix indicates lead-free)
Process Technology CMOS, EEPROM-based —
Logic Elements / Macrocells — 160 macrocells
Logic Array Blocks (LABs) — 4
User I/O Pins — 64 (also reported as 60 or 36 depending on variant)
Pin-to-Pin Delay (tPD) — 10 ns
Counter Speed (fCNT) — up to 175.4 MHz
Maximum Operating Frequency — 100 MHz
Supply Voltage - Core (VCC) — 5.0 V
I/O Supply Voltage (VCCIO) — 3.3 V or 5.0 V
Configuration Memory — EEPROM (non-volatile)
In-System Programming — Yes, via IEEE Std. 1149.1 JTAG
Program / Erase Cycles — 100 minimum
Data Retention — 20 years minimum
패키지 — 84-pin PLCC (J-lead, surface mount)
Operating Temperature Grade — Commercial (0C to +70C)

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