EPM7256ATI144-10 - 256-Macrocell CPLD, 3.3V, 144-TQFP | Altera
MPN: EPM7256ATI144-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $14.05 | $1,405.00 |
| 500 | $12.4 | $6,200.00 |
| 1,000 | $10.95 | $10,950.00 |
Drop-in alternatives for EPM7256ATI144-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7256AETI144-7
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View Datasheet βEPM7256AETI144-7N
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View Datasheet βEPM7256AQI208-10
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View Datasheet βEPM7256AQC208-7
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View Datasheet βEPM7256AETC144-10
β Drop-Inβ In Stock
$31.4 / Unit
View Datasheet βEPM7256AETC144-7N
β Drop-Inβ In Stock
$29.75 / Unit
View Datasheet βEPM7256ATI144-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Macrocells | 256 |
| Logic Array Blocks (LABs) | 16 |
| Maximum Usable Gates | 5,000 |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Maximum Frequency (fCNT) | 93.5 MHz |
| User I/O Pins | 100 |
| Supply Voltage (VCCINT) | 3.3 V |
| I/O Voltage (VCCIO) | 2.5 V or 3.3 V |
| Program Memory Type | EEPROM (non-volatile) |
| In-System Programming | Yes (IEEE 1149.1 JTAG) |
| Package | 144-pin TQFP |
| Operating Temperature Range | -40C to +85C (Industrial) |
| Mounting Type | Surface Mount |
| RoHS Status | Non-compliant (legacy Altera marking) |
| Process Technology | EEPROM-based CMOS |
EPM7256ATI144-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | GND β Ground |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | TDI β JTAG Test Data In |
| Pin 15 | TMS β JTAG Test Mode Select |
| Pin 16 | TCK β JTAG Test Clock |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | VCCIO1 β I/O bank 1 supply (2.5V or 3.3V) |
| Pin 22 | I/O β User I/O pin (bank 1) |
| Pin 23 | I/O β User I/O pin (bank 1) |
| Pin 24 | I/O β User I/O pin (bank 1) |
| Pin 25 | I/O β User I/O pin (bank 1) |
| Pin 26 | I/O β User I/O pin (bank 1) |
| Pin 27 | GND β Ground |
| Pin 28 | I/O β User I/O pin (bank 1) |
| Pin 29 | I/O β User I/O pin (bank 1) |
| Pin 30 | I/O β User I/O pin (bank 1) |
| Pin 31 | I/O β User I/O pin (bank 1) |
| Pin 32 | I/O β User I/O pin (bank 1) |
| Pin 33 | I/O β User I/O pin (bank 1) |
| Pin 34 | I/O β User I/O pin (bank 1) |
| Pin 35 | I/O β User I/O pin (bank 1) |
| Pin 36 | I/O β User I/O pin (bank 1) |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β User I/O pin (bank 1) |
| Pin 39 | I/O β User I/O pin (bank 1) |
| Pin 40 | I/O β User I/O pin (bank 1) |
| Pin 41 | I/O β User I/O pin (bank 1) |
| Pin 42 | I/O β User I/O pin (bank 1) |
| Pin 43 | I/O β User I/O pin (bank 1) |
| Pin 44 | I/O β User I/O pin (bank 1) |
| Pin 45 | I/O β User I/O pin (bank 1) |
| Pin 46 | I/O β User I/O pin (bank 1) |
| Pin 47 | GND β Ground |
| Pin 48 | I/O β User I/O pin (bank 1) |
| Pin 49 | I/O β User I/O pin (bank 1) |
| Pin 50 | I/O β User I/O pin (bank 1) |
| Pin 51 | I/O β User I/O pin (bank 1) |
| Pin 52 | I/O β User I/O pin (bank 1) |
| Pin 53 | I/O β User I/O pin (bank 1) |
| Pin 54 | I/O β User I/O pin (bank 1) |
| Pin 55 | I/O β User I/O pin (bank 1) |
| Pin 56 | VCCINT β Core supply (3.3V) |
| Pin 57 | I/O β User I/O pin (bank 2) |
| Pin 58 | I/O β User I/O pin (bank 2) |
| Pin 59 | I/O β User I/O pin (bank 2) |
| Pin 60 | I/O β User I/O pin (bank 2) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (bank 2) |
| Pin 63 | I/O β User I/O pin (bank 2) |
| Pin 64 | I/O β User I/O pin (bank 2) |
| Pin 65 | I/O β User I/O pin (bank 2) |
| Pin 66 | I/O β User I/O pin (bank 2) |
| Pin 67 | I/O β User I/O pin (bank 2) |
| Pin 68 | I/O β User I/O pin (bank 2) |
| Pin 69 | I/O β User I/O pin (bank 2) |
| Pin 70 | GND β Ground |
| Pin 71 | I/O β User I/O pin (bank 2) |
| Pin 72 | I/O β User I/O pin (bank 2) |
| Pin 73 | I/O β User I/O pin (bank 2) |
| Pin 74 | I/O β User I/O pin (bank 2) |
| Pin 75 | I/O β User I/O pin (bank 2) |
| Pin 76 | I/O β User I/O pin (bank 2) |
| Pin 77 | I/O β User I/O pin (bank 2) |
| Pin 78 | I/O β User I/O pin (bank 2) |
| Pin 79 | I/O β User I/O pin (bank 2) |
| Pin 80 | I/O β User I/O pin (bank 2) |
| Pin 81 | I/O β User I/O pin (bank 2) |
| Pin 82 | I/O β User I/O pin (bank 2) |
| Pin 83 | VCCIO2 β I/O bank 2 supply (2.5V or 3.3V) |
| Pin 84 | I/O β User I/O pin (bank 2) |
| Pin 85 | I/O β User I/O pin (bank 2) |
| Pin 86 | I/O β User I/O pin (bank 2) |
| Pin 87 | I/O β User I/O pin (bank 2) |
| Pin 88 | GND β Ground |
| Pin 89 | I/O β User I/O pin (bank 2) |
| Pin 90 | I/O β User I/O pin (bank 2) |
| Pin 91 | I/O β User I/O pin (bank 2) |
| Pin 92 | I/O β User I/O pin (bank 2) |
| Pin 93 | I/O β User I/O pin (bank 2) |
| Pin 94 | I/O β User I/O pin (bank 2) |
| Pin 95 | I/O β User I/O pin (bank 2) |
| Pin 96 | I/O β User I/O pin (bank 2) |
| Pin 97 | I/O β User I/O pin (bank 2) |
| Pin 98 | I/O β User I/O pin (bank 2) |
| Pin 99 | I/O β User I/O pin (bank 2) |
| Pin 100 | GND β Ground |
| Pin 101 | I/O β User I/O pin (bank 3) |
| Pin 102 | I/O β User I/O pin (bank 3) |
| Pin 103 | I/O β User I/O pin (bank 3) |
| Pin 104 | I/O β User I/O pin (bank 3) |
| Pin 105 | I/O β User I/O pin (bank 3) |
| Pin 106 | I/O β User I/O pin (bank 3) |
| Pin 107 | VCCIO3 β I/O bank 3 supply (2.5V or 3.3V) |
| Pin 108 | I/O β User I/O pin (bank 3) |
| Pin 109 | I/O β User I/O pin (bank 3) |
| Pin 110 | I/O β User I/O pin (bank 3) |
| Pin 111 | I/O β User I/O pin (bank 3) |
| Pin 112 | I/O β User I/O pin (bank 3) |
| Pin 113 | I/O β User I/O pin (bank 3) |
| Pin 114 | I/O β User I/O pin (bank 3) |
| Pin 115 | GND β Ground |
| Pin 116 | I/O β User I/O pin (bank 3) |
| Pin 117 | I/O β User I/O pin (bank 3) |
| Pin 118 | I/O β User I/O pin (bank 3) |
| Pin 119 | I/O β User I/O pin (bank 3) |
| Pin 120 | I/O β User I/O pin (bank 3) |
| Pin 121 | I/O β User I/O pin (bank 3) |
| Pin 122 | I/O β User I/O pin (bank 3) |
| Pin 123 | I/O β User I/O pin (bank 3) |
| Pin 124 | I/O β User I/O pin (bank 3) |
| Pin 125 | GND β Ground |
| Pin 126 | I/O β User I/O pin (bank 4) |
| Pin 127 | I/O β User I/O pin (bank 4) |
| Pin 128 | I/O β User I/O pin (bank 4) |
| Pin 129 | I/O β User I/O pin (bank 4) |
| Pin 130 | I/O β User I/O pin (bank 4) |
| Pin 131 | I/O β User I/O pin (bank 4) |
| Pin 132 | I/O β User I/O pin (bank 4) |
| Pin 133 | VCCIO4 β I/O bank 4 supply (2.5V or 3.3V) |
| Pin 134 | I/O β User I/O pin (bank 4) |
| Pin 135 | I/O β User I/O pin (bank 4) |
| Pin 136 | I/O β User I/O pin (bank 4) |
| Pin 137 | I/O β User I/O pin (bank 4) |
| Pin 138 | I/O β User I/O pin (bank 4) |
| Pin 139 | I/O β User I/O pin (bank 4) |
| Pin 140 | I/O β User I/O pin (bank 4) |
| Pin 141 | I/O β User I/O pin (bank 4) |
| Pin 142 | I/O β User I/O pin (bank 4) |
| Pin 143 | TDO β JTAG Test Data Out |
| Pin 144 | I/O β User I/O pin (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7256ATI144-10 is suitable for 6 applications: Telecommunications Infrastructure (DSLAM, Optical Transport), Industrial Automation and Motor Control, Medical Instrumentation, Military and Avionics Subsystems, ASIC and Processor Glue Logic Replacement, DSP and ASIC Peripheral Bridging.
Telecommunications Infrastructure (DSLAM, Optical Transport)
The EPM7256ATI144-10 fits telecom line cards and optical transport equipment where deterministic, instant-on glue logic bridges between ASICs, FPGAs, and backplane SERDES. Its 10 ns tPD handles address decoding, bus arbitration, and clock-domain crossing for T1/E1, SONET/SDH, and OTN framing with predictable timing that survives power glitches. The 100 user I/O pins comfortably route 8/16-bit datapath lanes plus control signals. The 3.3-V core with MultiVolt I/O simplifies interfacing to legacy 5-V-tolerant PHYs through external series resistors, and the non-volatile EEPROM configuration eliminates boot-PROM cost on hot-swap line cards.
Recommended
Industrial Automation and Motor Control
The EPM7256ATI144-10 is well-suited to PLCs, servo drives, and motor-control boards that demand the industrial -40C to +85C temperature range and instant power-up deterministic logic. Its 256 macrocells implement PWM generation, quadrature decoding, encoder fault handling, and fieldbus glue logic between microcontrollers and gate drivers. The JTAG ISP interface lets production engineers re-spin control firmware without removing the chip, which is critical for safety-locked motor control designs. The 10 ns tPD easily meets the 100 kHz to 200 kHz PWM update rates typical of three-phase inverter control loops.
Recommended
Medical Instrumentation
The EPM7256ATI144-10 serves medical instrument designers who need deterministic timing for patient monitoring, ultrasound beamforming front-ends, and infusion pump controllers. Its 10 ns pin-to-pin delay provides reliable timing for analog front-end sequencing, sample-clock generation, and isolated data-acquisition glue logic. The non-volatile EEPROM configuration means the device boots in known-good state on every power-up, eliminating risk of corrupted firmware in safety-critical care environments. Designers pair it with low-noise ADCs and DACs for portable diagnostic kits where low standby current and instant-on behavior are priorities.
Recommended
Military and Avionics Subsystems
The EPM7256ATI144-10 in its industrial temperature grade is widely used in legacy avionics, flight-control computers, and military radio systems where the MAX 7000A architecture has decades of proven reliability. The 256 macrocells handle MIL-STD-1553 and ARINC 429 bus interfacing, redundant-channel voting logic, and discrete I/O expansion for embedded SBCs. The instant-on non-volatile behavior ensures deterministic startup for safety-of-flight functions. Modern avionics upgrades pair this CPLD with radiation-tolerant FPGAs to provide reliable glue logic around the main processor complex, especially in DO-254 certifiable subsystems.
Recommended
ASIC and Processor Glue Logic Replacement
Designers replace discrete 74-series TTL/CMOS glue with the EPM7256ATI144-10 to consolidate address decoding, wait-state generation, chip-select logic, and bus multiplexing into a single non-volatile device. The 100 user I/O pins and 256 macrocells replace dozens of legacy logic ICs, shrinking the BOM and improving MTBF. The 3.3-V core and MultiVolt I/O interface seamlessly to legacy 5-V peripherals. For x86 and PowerPC embedded designs, the CPLD often handles ISA/PCI bus arbitration, ROM/RAM banking, and reset distribution with timing margins far tighter than discrete logic.
Recommended
DSP and ASIC Peripheral Bridging
The EPM7256ATI144-10 bridges DSP/ASIC peripherals such as EMIFA, HPI, McBSP, and external memory buses where deterministic latency and instant-on non-volatile behavior are required. With 10 ns tPD and 93.5 MHz fCNT, the part easily handles FIFO flag generation, address counter cascading, and DMA handshaking for TI TMS320 and Analog Devices SHARC designs. The JTAG ISP chain allows in-system reconfiguration during board bring-up, simplifying DSP firmware debugging. The MultiVolt I/O bank supports mixed-voltage peripherals in heterogeneous SoC designs.
Recommended
Recommended Products Summary
Engineering reference data for EPM7256ATI144-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7256AETI144-7 | EPM7256AETI144-7N | EPM7256AQI208-10 | EPM7256AQC208-7 | EPM7256AETC144-10 | EPM7256AETC144-7N |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 208-pin PQFP - different (larger) | 208-pin PQFP - different (larger) | 144-pin TQFP - same | 144-pin TQFP - same |
| Pin-to-Pin Delay (tPD) | 10 ns | 7 ns (faster) | 7 ns (faster) | 10 ns (same) | 7 ns (faster) | 10 ns (same) | 7 ns (faster) |
| Macrocells | 256 | 256 (same) | 256 (same) | 256 (same) | 256 (same) | 256 (same) | 256 (same) |
| Logic Array Blocks | 16 | 16 (same) | 16 (same) | 16 (same) | 16 (same) | 16 (same) | 16 (same) |
| Maximum Frequency (fCNT) | 93.5 MHz | 125 MHz (faster) | 125 MHz (faster) | 93.5 MHz (same) | 125 MHz (faster) | 93.5 MHz (same) | 125 MHz (faster) |
| Operating Temperature | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Lead Finish | SnPb (non-RoHS) | SnPb (non-RoHS) | Pb-free matte-tin (RoHS) | SnPb (non-RoHS) | SnPb (non-RoHS) | SnPb (non-RoHS) | Pb-free matte-tin (RoHS) |
| User I/O Pins | 100 | 100 (same) | 100 (same) | 164 (more) | 164 (more) | 100 (same) | 100 (same) |
Key Differentiators
- Drop-in speed-grade upgrade to 7 ns tPD on the same 144-pin TQFP (vs EPM7256AETI144-7)
- Pb-free RoHS-compatible lead finish available on identical die (vs EPM7256AETI144-7N)
- Larger 208-pin PQFP variant for high-I/O designs (vs EPM7256AQI208-10)
Design Notes
The EPM7256ATI144-10 requires four separate supply rails: VCCINT (3.3V core) and up to four VCCIO banks (2.5V or 3.3V each). Place a 0.1uF ceramic decoupling capacitor within 5 mm of every VCC pin, and add a bulk 10uF tantalum or ceramic cap per supply rail. Power-up sequencing is not required between VCCINT and VCCIO, but ramp time should be greater than 1 ms to ensure clean JTAG ISP initialization.
The 144-pin TQFP has a 0.4 mm lead pitch, requiring PCB land patterns compliant with IPC-7351 nominal-density standards. Use a 4-layer board with a dedicated ground plane directly beneath the CPLD to control impedance and provide thermal relief. Keep JTAG signals (TDI, TDO, TMS, TCK) routed with 50-ohm controlled impedance and length-matched within 25 mm if multiple devices share the JTAG chain.
Do not exceed 3.6V on VCCINT or VCCIO; absolute maximum stress will damage the EEPROM cells. When migrating designs from older MAX 7000 (non-A) parts, note that the MAX 7000A adds MultiVolt I/O banks - leaving a VCCIO bank unpowered while driving the I/O pins is unsafe. Always power unused VCCIO pins even if their I/O pins are tri-stated to prevent I/O leakage.
Compliance Information
Original Altera EPM7256ATI144-10 uses SnPb lead finish (non-RoHS). For RoHS compliance choose the N-suffix variant EPM7256ATI144-10N. AEC-Q100 not applicable β this is a commercial/industrial CPLD, not an automotive-grade part.
